I have some question about LVS

[owen_li]

Hi guys.

I have no experience on LVS, but I have a question about LVS run.

In my opinion, the mismatch between layout and schematic can be covered by DRC check. For example, if some pin is connected to some net by mistake, we can see the short by DRC run.

So is there any scenario that LVS can check but DRC not ?

Thanks very much~~~

 

[keith1200rs]

Absolutely! DRC just checks the process design rules. You could DRC a chip layout and it could pass but it doesn't mean you have the correct schematic - you could have the schematic for a completely different IC. Or, all the connectivity could be correc but the transistor sizes could be completely wrong. You could put an NMOS in place of a PMOS and pass DRC but it wouldn't be the right schematic.

LVS and DRC are totally different. LVS checks that the layout matches the schematic. DRC checks that layout meets the process design rules - that is all.

Keith.

 

[nav_vlsi]

DRC checks only for polygon rules - spacing , overlap , width etc. It cannot TRACE the connectivity. Assume that , a net travels through 3 layers to reach the pin, now DRC can check individual layer rules for spacing, width etc. but It cannot trace or track connectivity through multiple layer. assume there is connectivity loss in layer 2(forgot to put a via). now the layout can be clean from DRC perspective . but will have an LVS error because of missing connectivity.

 

[lostinxlation]

In my opinion, the mismatch between layout and schematic can be covered by DRC check. For example, if some pin is connected to some net by mistake, we can see the short by DRC run.

OK, here are some questions for you.
Did you read schematics when you ran DRC last time ?
What does LVS stand for ?