I have some problem with my xilinx 12.1 software

[velu.plg]

i have some problem with my xilinx 12.1 software

during check syntax process (for any simple programs) it gives failer response

this is my and gate program....

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity a is
    Port ( a : in  STD_LOGIC;
           b : in  STD_LOGIC;
           c : out  STD_LOGIC);
end a;

architecture Behavioral of a is

begin
c <= a and b;

end Behavioral;

error:

Started : "Check Syntax for a".
INFO:HDLCompiler:1061 - Parsing VHDL file "F:/vlsi project/AV00 _samplecode/vhdl basic/test/a.vhdl" into library work
INFOrojectMgmt:656 - Parsing design hierarchy completed successfully.
Running xst...
Command Line: xst -intstyle ise -ifn {F:/vlsi project/AV00 _samplecode/vhdl basic/test/a.xst} -ofn a.stx

=========================================================================
* HDL Compilation *
=========================================================================
Compiling vhdl file "F:/vlsi project/AV00 _samplecode/vhdl basic/test/a.vhdl" in Library work.
Entity <a> compiled.
Entity <a> (Architecture <Behavioral>) compiled.

Process "Check Syntax" failed

 

[TrickyDicky]

Re: problem with xilinx .....................

You cant have the entity called a and a port called a in the same entity

 

[FvM]

Re: problem with xilinx .....................

No syntax error visible. There should be an error line and a qualified error messsage.

May be your tool doesn't like the entity name repeated as a port name.

 

[velu.plg]

now i change my entity name , but error is their.

entity test12 is
    Port ( a : in  STD_LOGIC;
           b : in  STD_LOGIC;
           c : out  STD_LOGIC);
end test12;

architecture Behavioral of test12 is

begin
c <= a and b;

end Behavioral;

 

[TrickyDicky]

Assuming you have the std logic 1164 package included, there is no syntax error. Are you sure this is the only code in the project