I have negative slack after CTS, what is the problem in my sdc?

[yilmi shin]

in my sdc
create_clock CLK_A
create_generated_clock CLK_B -divide 1
create_generated_clock CLK_C -divide 7

in my design
CLK_A - BUF -> CLK_B

CLK_B feed u_count_X
CLK_B feed u_ff_m
CLK_C is u_ff_m/Q
CLK_C feed u_carry_X
u_ff_m/D is the combinational logic using u_count_x/Q
u_count_x/D has the combinational logic using u_carry_X/Q

after CTS,
u_count_X/CK has several inverters/buffers from CLK_B
the delay of u_count_X/CK is 804ps
the delay of u_ff_m/D is 1718 ps

but
u_ff_m/CK has no inverters/buffers from CLK_B
the delay of u_ff_m/CK is 79ps

so i have negative slack !!!

what is my fault?

 

[sam536]

nothing to do with SDC. Check the skew between those points. If its too high, inform to CTS engineer. If combo logic between Pre-CTS and Post-CTS is too high, check the reasons. Is fanout is more or cap is increased?.

you see some negative slacks after CTS . Need analysis for this. If you can share the timing report, I can tell you the issues need to revisit for further analysis.

 

[morris_mano]

in my sdc
create_clock CLK_A
create_generated_clock CLK_B -divide 1
create_generated_clock CLK_C -divide 7

Just curious, don't you have to specify the source clock when defining generated clock in SDC, or is it automatically inferred?

I usually specify generated clock as

create_generated_clock -name xxx -source xxx -multiply_by x -divide_by x [get_pin xxx]

 

[yilmi shin]

Thanks for your attention !!

CTS engineer checked the reasons.
this design had the feedback loops. it is not recommended. but I just implemented the design as the algorithm.
CTS engineer guess ; because of the loop, u_count_x/CK has too many inverters/buffers after CTS.
So, I changed the design has only CLK_A clock.
In DC, the slack is just met, slack is 0.
I'm waitng PnR result.

once agin, thank you so much.

 

[morris_mano]

this design had the feedback loops. it is not recommended..

Not sure what tool you are using but during synthesis the tool will try to break the combination feedback loop with loop breaker. One way to find out during synthesis( CADENCE rtl compiler), if your design has combination loop or not is to do following

report cdn_loop_breaker > $_REPORTS_PATH/${DESIGN}_loop_breaker.rpt

This report will tell you where the loop is.