I have a resetting issue in video system using kintex-7 FPGA board

[biju4u90]

Resetting issue in video system using kintex 7 FPGA board

I am trying to generate a basic video system in kintex 7 FPGA board. The system contains 2 VDMAs and a test pattern generator to generate the video pattern. Vivado IPs are used in the system. I get the output when I program the FPGA for the first time (ie. power on). But the pattern doesn't get generated in the output when I reset the FPGA using the reset button in the board. I have done pin mapping for the reset button. What could be the possible reasons?

 

[Jaseel]

Re: Resetting issue in video system using kintex 7 FPGA board

Please see the VDMA register status to find the possible error.

 

[ads-ee]

Re: Resetting issue in video system using kintex 7 FPGA board

How did you handle the reset button input in your design?

Did you first debounce it and then synchronize it to the various clock domains?

 

[biju4u90]

Re: Resetting issue in video system using kintex 7 FPGA board

Did you first debounce it and then synchronize it to the various clock domains?

What do you mean by debouncing the reset system?? How can I achieve it?

I am having a system clock going to MIG and the mig clock out is fed to a clock generator for two clocks - one running at 100MHz and other at 148.5MHz. I am using three process reset systems. One reset system for MIG, second one for the 100MHz clock domain and the third one for the 148.5MHz domain. Microblaze system runs at 100MHz and the video ips run at 148.5MHz.

 

[nsgil85]

Re: Resetting issue in video system using kintex 7 FPGA board

Hi

You can find information about debouncing block in:
https://eewiki.net/pages/viewpage.action?pageId=4980758

Gil

 

[std_match]

Re: Resetting issue in video system using kintex 7 FPGA board

You can find information about debouncing block in:
https://eewiki.net/pages/viewpage.action?pageId=4980758

The debouncing block from that link has 3 FF's (registers) plus a 19-bit counter, in total 22 registers, per input.

It is important to make a distinction between "debouncing" and "noise filtering".
Debouncing is to remove the noise/glitches that occur when the signal from the switch/contact goes from '0' to '1' or from '1' to '0'.
Noise filtering is to remove noise/glitches that can occur at any time, even when the signal is stable.

Noise filtering is more complex, and the 23-register "debouncing block" from the link is really a "noise filter".

Debouncing can be done in a much simpler way. If the signal is sampled with a period longer than the "bounce time" (which is typically less than 10 ms) the output will be clean (after a meta-stability synchronizer). It is then enough to have one global "switch sample" strobe and only 3 registers per input.
2 registers are the normal meta-stability synchronizer and one register is the sample memory. It should be possible to use only two registers to implement both functions, but it is easy to make a mistake.

This will save a lot of logic if there are many inputs from mechanical switches, and if "noise filtering" isn't needed.

If noise filtering is needed for many inputs, the counters should be divided into a global counter and per input local counters.
As an example, the global counter can create strobes with a period time of 4 ms. Then it is enough to have a 3-bit counter per input to get 28-32 ms filtering (uncertain to 4 ms because the random relation between the input and the 4 ms strobe).