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I have a question about the linearity of the MOSFET's state.

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boramm

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I would like to compare the linearity when the TR switch is in the ON/OFF state of the nMosfet of the conventional tsmc cmos process as follows. At this time, in general, when on-state and off-state, in which state would linearity be better?

Is this something that can only be learned through simulation?

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