I have a question about # delay!!

[Daniel M.E. Lee]

While I simulate my design, I meet some trouble.

In my RTL code(verilog), there is # delay statement like as below.

assign #1 DMAReady = iDMAReady;

At wave viewer, DMAReady signal has unknown value.

Did you have experience about that, friends?
Does it related tool's option?

FYI,
I'm using
Verilog-HDL as RTL-code,
ncverilog as complier,
and Verdi as simulator.

Plz help me!!

Thank you for reading my post!!

 

[quan228228]

pls delete your INC* directory in your simulation directory, then run again.

It is not your code fault. It is just a bug for NC-verilog. sometime you must delete the old files and directory generated by previous simulation.


David

 

[Daniel M.E. Lee]

I found the reason why # delay does not work.

If we use # delay, we states time like # 1, # 30 and etc.
But unless we did not describe timescale, ncverilog cannot decide how many times it delay. So we must describe like as below.

`timescale 1ns/10ps or other unit

Anyway, thank you for your help, David.

 

[nileshprasad]

Thank you!!.. Daniel