I am trying to synthesize a code in xilinx ISE 9.2i .I am getting the following error

[krishna2728]

Xst:528 - Multi-source in Unit <pcd> on signal <pcd_state<3>>
Sources are:
Output signal of FD instance <pcd_state_ren_3>
Output signal of FD instance <pcd_state_3>


what does this error mean and how to rectify it


thank you in advance

 

[xtcx]

Simple, You are driving two sources FFs into one sink FF such as pcd_state register. Check your code for the input of this signal pcd_state for which you may be driving inputs at two different places or in modules.

Or display your code here, we will point out.

see this post in xilinx forums

Xst:528 - Multi-source in Unit on signal; this sig... - Xilinx User Community Forums

You will get the idea of proper coding. Hope it helps

 

[krishna2728]

yaa but i have to drive two sources how can i drive two sources can i give delay in RTL design ??

 

[xtcx]

Please can you explain a bit more?.
I could only partially understand your statement.
If you drive two sources by writing consecutive statement like this, only the last statement will be considered. In this case, it is '0'.

pcd_state<3> <= '1';
pcd_state<3> <= '0';

Instead if you want some RTL delay, write it like

pcd_state<3> <= '1';
wait <RTLDelay>
pcd_state<3> <= '0';

But this works only for simulation. RTL delays are only possible using clock based sequential logics.

 

[krishna2728]

yaa i need to include some RTL delays .As in my code i have to give the output of one module as input to another and i have declare with same names in both the modules which maybe reason for this error

can i synthesize when i use delays??

 

[jducluzeau]

Delays will not be synthesized.

 

[xtcx]

First tell me what do you mean by delay here. Just try to describe things in detail, that will help get you the right answer. I'd say it's rather confusing than answering your question.

Post your sample code, so that it will be a bit easy to check the cause of error.