I am learning to use Cadence by designing an energy recovery inverter circuit

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shipra_2

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Hi
I am learning to use Cadence by designing an energy recovery inverter circuit.
I'm a bit stuck understanding what these error messages mean in the DRC checker.
if there is a link where I can find an explanation please let me know, otherwise I'd really appreciate some help understanding the following:

1. Welnotr_StampErrorFloat
(NWEL is highlighted)

2. 4:16n Maximum N+ Diffusion to nearest P+ pick-up spacing (inside P-Well or T-Well) is 20um
all nmos diffusion highlighted
 

shipra_2 said:
1. Welnotr_StampErrorFloat
(NWEL is highlighted)
Click to expand...

NWELL tap not present, or not connected to pos. potential (VDD), and/or not connected by metal.

shipra_2 said:
2. 4:16n Maximum N+ Diffusion to nearest P+ pick-up spacing (inside P-Well or T-Well) is 20um
all nmos diffusion highlighted
Click to expand...

A P+ pick-up (substrate or P- or T-Well P+ tap, i.e. the bulk connection of NMOS transistor(s)) is too far (> 20µm) from the NMOS source & drain diffusion regions.
 

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