hysteresis loop in positive feedback latch circuit

[anne rachel]

Hi everyone,


Could anyone suggest me as to how to analyse the hysteresis loop of a positive feedback latch circuit? i need the small signal analysis of the circuit and the conditions to avoid hysteresis loop...if possible ,please post any material required for the same..thanks in advance ...

 

[FvM]

To avoid hysteresis, you'll cancel positive feedback...
No idea what you want to achieve.

It might be helpful if you tell what kind of latch circuit you imagine.

 

[anne rachel]

To avoid hysteresis, you'll cancel positive feedback...
No idea what you want to achieve.

It might be helpful if you tell what kind of latch circuit you imagine.

View attachment cal of hysterisis.pdf

Hi,

thanks for the reply.
I have attached the pdf file which has discussed about the hysteresis in positive feedback latch circuit.. but I didn' t understand how they have come up with design specifications of the comparator with and without hysteresis...if possible,could u kindly help me out in understanding such design specs?thank you ...

 

[FvM]

The paper compares design with high and low hysteresis, not comparators without hysteresis. Unfortunately it doesn't compare the static transfer functions that show the "hysteresis loop".

Hysteresis can be adjusted by varying the positive feedback factor, in this case by scaling the area of cross-coupled transistors.

As another comment, there's no reasonable purpose in performing small signal analysis of bistable circuits.