Hummingbird Algorithm nexys 2 500(FPGA Implementation)

[leohawk88]

Hi all,

I need some help with hummingbird cryptographic algorithm. I have developed the ecryption and decryption in ise 12.3.

I need help with implementing it on the FPGA nexys 2 xcs500. My output's are assigned to the LED's. But it does not match the simulation. Every time I program the .bit file through adept, my results keep changing on the board(led's outputs are not fixed and keep changing).

I thought the issue was with the clock which is fixed at 50Mhz. I used a divider to run at 1Mhz. Now my output remains the same but is not matching the simulation.

I am new to VHDL, forgive me for any wrong technical terms or phrases.

Please help ASAP.

Thanks in advance.

Leo

 

[TrickyDicky]

How have you divided the clock? did you write a clock divider (bad) or use clock enables (good)?

How about posting some code and talking about specific problems.

 

[leohawk88]

Hi Tricky,

Thanks for such a prompt reply. My clock divider is as follows,

divideclock: process(clk)

variable divider : std_logic_vector(7 downto 0):="00000000";
Variable sig: std_logic:='0';

begin
if( clk='1' and clk'EVENT) then

divider := divider + '1';

end if;


if(divider=00110010)then
clock <= not sig;
divider:="00000000";
end if;

end process;

 

[TrickyDicky]

yes, thats the bad method.
But in your code clock is constant '1', because sig is never set to anything

But you should create clock enables instead, not an actual clock.

 

[leohawk88]

Tricky,

I am working on clock enable and will implement it soon. May I ask you to provide me with some resources or links on clock enable. In the mean time, I will search on my own as well.

Thanks again

Leo

 

[TrickyDicky]

Clock enables are just a signal generated that will enable a circuit for a specified period of time. You run the circuit using the system clock, but you only enable it for, say, 1 in every 3 clocks.

Here is an example using a counter to generate a 1/4 clock enable

signal cnt : unsigned(1 downto 0);

process(clk, reset)
begin
  if reset = '1' then
    cnt <= "00";
  elsif rising_edge(clk) then
    if cnt = 0 then
       --do something once every 4 clocks
    end if;

    cnt <= cnt + 1;
  end if;
end process;