Hspice-wrong results

[mhjedaboard]

Salaam every body,
this is the circuit:



========================
I wrote these lines for the circuit:

.prot
.lib 'mm018.l' TT
.unprot

Vdd 1 0 DC 1.8V
Ibias 2 0 dc 1ma

Cout 6 0 100ff
M2 4 2 1 PMOS L=0.18u W=4u
M4 5 2 1 PMOS L=0.18u W=30u
M6 6 2 1 PMOS L=0.18u W=45u
M7 2 2 1 PMOS L=0.18u W=45u
M1 4 3 0 NMOS L=0.18u W=4u
M3 5 4 0 NMOS L=0.18u W=45u
M5 6 5 0 NMOS L=0.18u W=30u

.op
.OPTION CAPTAB
.prob
.end

=========================
from ".lis" output file, the operation currents are:

element	m2	m4	m6	m7	m1	m3	m5
model	pmos.6	pmos.3	pmos.3	pmos.3	nmos.6	nmos.3	nmos.3
region	Linear	Saturati	Linear	Saturati	Cutoff	Linear	Cutoff
id	-99.1687u	-1.279m	-1.046m	-1.648m	58.7580p	1.2795m	845.2648p

======================
my first problem is that why id3 is more than 1ma ?
there should be 1ma for every transistor because of current mirrors.

 

[dick_freebird]

Simple current mirrors, especially at short channel length,
are far from ideal and have a strong voltage dependence.
Only when Vds(1)=Vds(2) can you expect such a mirror
to produce Ids(1)=Ids(2) even with ideal matching. In your
current-loaded inverter chain you can expect this to not
often be the case unless it's held linear by feedback or you
force the perfect input operating point.

Then you have various mirror widths all mismatching the
reference device (M7, but it looks to me like maybe the
names as well as the parameters are off). They certainly
do not match the legend on the schematic plot.

Now I also see two pmos models called out in the table,
but I see neither "pmos.6" nor "pmos.3", only "PMOS"
called out in the text and wonder why the inconsistency
and whether you are providing an accurate description
of the problem as it sits. For that matter, such simple
names are in my experience unusual (unless this is some
sort of simple teaching models set - real foundries tend
to have multiple MOS device types and structures and
so a more elaborate naming convention).

 

[mhjedaboard]

Simple current mirrors, especially at short channel length,
are far from ideal and have a strong voltage dependence.
Only when Vds(1)=Vds(2) can you expect such a mirror
to produce Ids(1)=Ids(2) even with ideal matching. In your
current-loaded inverter chain you can expect this to not
often be the case unless it's held linear by feedback or you
force the perfect input operating point.

thanks a lot dick_freebird,
its my homework and I want to analyze it with hand writing and with hspice.
and I'm very weak in both. :-?
so, you think the hspice answers are OK?

Then you have various mirror widths all mismatching the
reference device (M7, but it looks to me like maybe the
names as well as the parameters are off). They certainly
do not match the legend on the schematic plot.

the names of devices are provided by our teaching assistant.

Now I also see two pmos models called out in the table,
but I see neither "pmos.6" nor "pmos.3", only "PMOS"
called out in the text and wonder why the inconsistency
and whether you are providing an accurate description
of the problem as it sits.

For that matter, such simple
names are in my experience unusual (unless this is some
sort of simple teaching models set - real foundries tend
to have multiple MOS device types and structures and
so a more elaborate naming convention).

this was another of my problems.
I don't know why models are different while i have input same for all.

 

[dick_freebird]

Perhaps there are, but you need to fix your structural
problems first (for starters, why does the "netlist"
mismatch the schematic picture), get to where you are
not fighting built-in discrepancies of your own making
and maybe then someone can help you with -an-
analysis (as opposed to endless what-about? type
questions that do not converge on anything).

Schematic:netlist agreement must be the start of any
useful SPICE analysis, and until you know you have that
even a hand analysis (schematic based) must be suspect.
Which (if either) is the "golden" expression of the circuit?
Since it appears both are handed to you, and the two
do not agree, perhaps this problem has to be attacked
at its source.