HSpice vs Cadence Virtuoso

[oAwad]

I would like to know the difference between digital circuit simulation in HSpice and cadence virtuoso. If I have a digital layout designed using encounter and I want to perform transient time simulations, crosstalk simulations and monte carlo simulations, why would some people go for HSpice over Virtuoso ?

I want to know the general differences and which would be more suitable for the mentioned tasks.

Thanks

 

[jbeniston]

HSpice is a simulator - Virtuoso is a schematic / layout design program. The Cadence simulator is Spectre.

HSpice and Spectre basically do the same thing, so you could use either.

 

[dick_freebird]

Believe HSpice is tied to some non-Cadence EDA platforms
(at least optionally).

Digital circuits, you would not really want to use either one
(other than some parametric simulations). Certainly not to
do functional verification with a deep set of vectors. Hard
to apply, to criticize and a hella wait.

Cadence has a pretty good mixed signal functionality,
co-simulation using Spectre and verilog. Not sure what
HSpice has going, to simulate analog and large digital
together. But I'd bet that whatever EDA platforms tie in
HSpice, has some sort of facility for it. How good, can't
say.

 

[ThisIsNotSam]

Believe HSpice is tied to some non-Cadence EDA platforms
(at least optionally).

Digital circuits, you would not really want to use either one
(other than some parametric simulations). Certainly not to
do functional verification with a deep set of vectors. Hard
to apply, to criticize and a hella wait.

Cadence has a pretty good mixed signal functionality,
co-simulation using Spectre and verilog. Not sure what
HSpice has going, to simulate analog and large digital
together. But I'd bet that whatever EDA platforms tie in
HSpice, has some sort of facility for it. How good, can't
say.

hsim has support for mixed mode simulation just like spectre does. it runs hspice under the hood for the 'analog' part.

I would argue that hspice is the industry preferred tool and certainly used more often to characterise IP.

 

[oAwad]

Believe HSpice is tied to some non-Cadence EDA platforms
(at least optionally).

Digital circuits, you would not really want to use either one
(other than some parametric simulations). Certainly not to
do functional verification with a deep set of vectors. Hard
to apply, to criticize and a hella wait.

Cadence has a pretty good mixed signal functionality,
co-simulation using Spectre and verilog. Not sure what
HSpice has going, to simulate analog and large digital
together. But I'd bet that whatever EDA platforms tie in
HSpice, has some sort of facility for it. How good, can't
say.

hsim has support for mixed mode simulation just like spectre does. it runs hspice under the hood for the 'analog' part.

I would argue that hspice is the industry preferred tool and certainly used more often to characterise IP.

Thank you both for your replies.
let's be precise, I have a digital VLSI design where its inputs are digital signals and have some digital and analog outputs. So how can I simulate this design ? Is there a possible way to generate an input stream of bits in cadence virtuoso ?

Its an encryption core so it has a bunch of input stream bits (data and key), output cipher stream and some ANALOG outputs. any suggestions ?

 

[pancho_hideboo]

Is there a possible way to generate an input stream of bits in cadence virtuoso ?

Still you can not understand anything at all.

Cadence Virtuoso is a design framework.
You can launch various simulators such as HSPICE, eldo, ADSsim, etc. from Cadence Virtuoso.

Make clear followings.

(1) Input Netlists.
SPICE Format ?
Spectre Format ?
Verilog-HDL ?

(2) Stimulus
VCD File ?
PWL File ?

(3) Measurements
What type of measurement do you want to do ?
What post processing tool do you want to use ?
What data format do you want to treat as output ?

 

[oAwad]

Still you can not understand anything at all.

Cadence Virtuoso is a design framework.
You can launch various simulators such as HSPICE, eldo, ADSsim, etc. from Cadence Virtuoso.

Make clear followings.

(1) Input Netlists.
SPICE Format ?
Spectre Format ?
Verilog-HDL ?

(2) Stimulus
VCD File ?
PWL File ?

(3) Measurements
What type of measurement do you want to do ?
What post processing tool do you want to use ?
What data format do you want to treat as output ?

I have designed a layout (in SoC encounter) for a core that takes a digital input stream and outputs a digital stream as well as an analog signal. Now, I want to simulate the two outputs with respect to time. I will use cadence spectre tool. The input netlist would be SPICE format. The stimulus would be vbit source into which I want to load a bit stream from a text file.

I have two questions:

1) How to get the SPICE netlist out of my design in Encounter ? (Should I transfer the design to Virtuoso first using GDSII ?)

2) Will I be able to simulate the output digital bit stream and the other output analog signal with respect to time using this way ? (I would like to have the two outputs on same graph vs time so that I can compare the two outputs).

If there is an easier way, please suggest it.

Thank you

 

[ThisIsNotSam]

export a gds from encounter, extract a spice netlist, then run the simulation. you should be able to see both analog and digital signals. spice doesn't know what a 'digital' signal is. everything is Rs and Cs (sometimes Ls).

 

[oAwad]

export a gds from encounter, extract a spice netlist, then run the simulation. you should be able to see both analog and digital signals. spice doesn't know what a 'digital' signal is. everything is Rs and Cs (sometimes Ls).

Thanks. Does the GDS file include all parasitics or I should include SDF file during simulation ?

 

[ThisIsNotSam]

Thanks. Does the GDS file include all parasitics or I should include SDF file during simulation ?

again, you are very very lost. GDS is a design format, it doesn't hold any parasitics. It can be used to generate parasitics by doing extraction. SDF is a completely unrelated file format. SDF goes with verilog, spice doesn't go with SDF.

 

[oAwad]

again, you are very very lost. GDS is a design format, it doesn't hold any parasitics. It can be used to generate parasitics by doing extraction. SDF is a completely unrelated file format. SDF goes with verilog, spice doesn't go with SDF.

Thank you and forgive me for my ignorance since I'm an undergrad.....I want to include the effect of geometric structure and parasitics of the layout in simulation, so is it already included in the extracted SPICE or I should add it to Spectre in a certain way ?

 

[ThisIsNotSam]

it is included in the extracted spice. that is the whole point of having an extracted netlist.

 

[pancho_hideboo]

2) Will I be able to simulate
the output digital bit stream
and the other output analog signal
with respect to time using this way ?

Yes.
There is no difference between analog and digital signal in SPICE Type simulators.

I think your simulation is no more than analog simulation as far as seeing from simulator.

(I would like to have the two outputs on same graph vs time so that I can compare the two outputs).

You can plot them, even if you use cosimulation between SPICE type simulator and Event-Driven type simulator(such as NCsim, VCS, etc.).