Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

HSPICE sram 6t cell design

Status
Not open for further replies.

zorjak

Newbie level 3
Joined
May 9, 2009
Messages
4
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,304
Hello guys,

I am new with HSPICE and I started with 6t transistor cell design.

I used this code for simulation of sram cell
Code:
"SRAM cell 6T

.LIB "ptm_16nm.lib" predictive_16_lp
.LIB "ptm_32nm.lib" predictive_32_lp

.lib ".\Libraries\ptm_16nm.lib" predictive_16_lp
.lib ".\Libraries\ptm_16nm.lib" predictive_16_hp

.lib ".\Libraries\ptm_22nm.lib" predictive_22_lp
.lib ".\Libraries\ptm_22nm.lib" predictive_22_hp

.lib ".\Libraries\ptm_32nm.lib" predictive_32_lp
.lib ".\Libraries\ptm_32nm.lib" predictive_32_hp

**mos transistors - latch
m1 Q QR 0 0 nmos_22nm_hp  w=88n  l=22n
m2 Q QR 1 0 nmos_22nm_hp  w=88n  l=22n
m3 QR Q 0 1 pmos_22nm_hp  w=33n  l=33n
m4 QR Q 1 1 pmos_22nm_hp  w=33n  l=33n

**mos transistors - data access
m5 BL wl Q nmos_22nm_hp 	w=44n  l=22n
m6 BLR wl QR  nmos_22nm_hp  w=44n  l=22n

.param pulse_period = 50ns
.param pulse_width = 4ns
.param pulse_delay = 2ns
.param pulse_rise = 100ps
.param pulse_fall = 100ps


*sources supply
vdd 1 0 dc 0.95

** access control
vwl wl 0 pulse(0 0.95 pulse_delay pulse_rise pulse_fall pulse_width pulse_period)

**data
vbl BLR1 0 dc 0.95 
vblr BL1 0 pulse(0.95 0 pulse_delay pulse_rise pulse_fall pulse_width pulse_period)

**control
vr_w r_w 0 pulse(0 0.95 pulse_delay pulse_rise pulse_fall pulse_width pulse_period)



*devices switches
GBL BLR1 BL VCR PWL(1) r_w, 0 0v, 1e20 0.95v, 1.00000E-20
GBLR BL1 BLR VCR PWL(1) r_w, 0 0v, 1e20 0.95v, 1.00000E-20


*analysis
.tran 0.01n 50n start = 0
*.print tran v(BL) V(BLR)
.option post
.end

"

However, when I run simulation I get some warrings:
Warning: Acde = 1 may be too small in BSIM4 model nmos_22nm_hp with w=8.8e-008 l=2.2e-008.

Warning: (B1 + Weff) may be too small in BSIM4 model nmos_22nm_hp with w=8.8e-008 l=2.2e-008.

Warning: Acde = 1 may be too small in BSIM4 model nmos_22nm_hp with w=4.4e-008 l=2.2e-008.

Warning: (B1 + Weff) may be too small in BSIM4 model nmos_22nm_hp with w=4.4e-008 l=2.2e-008.

Warning: Acde = 1 may be too small in BSIM4 model pmos_22nm_hp with w=3.3e-008 l=3.3e-008.

Warning: (B1 + Weff) may be too small in BSIM4 model pmos_22nm_hp with w=3.3e-008 l=3.3e-008.

Can anyone explain me what this Acde = 1 means I don't understand and this B1+Weff? What is this? how can I know what is the limit of this value?

thanks for any kind of help. It would be useful really.


regards
Zoran
 
Last edited by a moderator:

Hi,

I'm new to HSPICE as well, and I'm facing this warning and don't know if its affecting my results or just one of those harmless warnings.

Have you figured it out yet? Anyone else that has any idea about this?


Thanks,
 

very useful link link.

thank you tariq.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top