when I simulate,the report says "timestep too small".
one suspicious warning is because I connected all nodes of one transistor together.
how should I deal with this?
Hi,
1. You could add:" .option gshunt=1e-14 and cshunt=1e-14" into the top of sim file. It coukd be useful
2. If it doesn't help, You can look at in the list file (at the end of list file) then see the point that spice announce timestep too small. You could find some thing relative convergence problem, forexample, you have some devices (as fuses) that their nodes are connected togetther.
That is my way to solve the problem that sometimes I got. Good luck!
Hi,
1. You could add:" .option gshunt=1e-14 and cshunt=1e-14" into the top of sim file. It coukd be useful
2. If it doesn't help, You can look at in the list file (at the end of list file) then see the point that spice announce timestep too small. You could find some thing relative convergence problem, forexample, you have some devices (as fuses) that their nodes are connected togetther.
That is my way to solve the problem that sometimes I got. Good luck!
hi harrytrinh,
I added the ".option gshunt=1e-14 and cshunt=1e-14"but it doesn't help.
meantime I found 3 nodes claiming non-convergence at the lis file.
Acctually these 3 nodes are the voltage sources within package model.
and yes,there are many devices whose nodes are connected together,but those devices are right be they should,I can't change them.
How should I deal with them?
If you add the package model, try to add a small resistor in your power rail , say 1 ohm or 2 ohm, to decrease the Q factor of L of package model. Thease small resistor can be modeled as your metal line resistance, I thank that will not affect your ciecuit simulation accuracy and help your circuits convergence.
the non-convergency is a very "irksome" problem, when i simulate the whole circuit system, i encount this problem. who have a detailed experience to share about this?
Hey try and see if you are trying to ramp up your voltage sources too fast. Internal time step algorithm is used by HSPICE to extrapolate to the next voltage or current. If there is a sudden ramp in the voltage or current in any node, then it will give an internal timestep error.
Rather than changing GMINDC and G/C-SHUNT (which are used in high-frequency) try and type METHOD=GEAR. I think that GEAR method solves better than TRAP(trapezoidal).