Peter Chang
Junior Member level 2
Dear Sir,
I'm running a co-sim by using hsim & ncverilog. Analog circuit is written in spice netlist.
And digital circuit is in verilog. After running, some error message found as below.
Error: parameter "pwr" not found for instance
xsdi_rx_top.xtenbit_sdi_rx_topall.xtenbit_sdi_rx_top.xrx_sdi.xrxpll_yx_sdi.xlcvco_sdi_rx.xi18
Error: parameter "pwr" not found for instance
xtenbit_sdi_rx_topall.xtenbit_sdi_rx_top.xrx_sdi.xrxpll_yx_sdi.xlcvco_sdi_rx.xi18
Error: Netlist compilation failed!
pwr is a build-in function for hsim. Why it doesn't pass the compilation? Thanks
XI18 is a subcircuit as below. It is a varactor, PVAR12_CKT_RF.
XI18 P PUMP PVAR12_CKT_RF L=0.5U W=5U NF=4
Peter Chang
I'm running a co-sim by using hsim & ncverilog. Analog circuit is written in spice netlist.
And digital circuit is in verilog. After running, some error message found as below.
Error: parameter "pwr" not found for instance
xsdi_rx_top.xtenbit_sdi_rx_topall.xtenbit_sdi_rx_top.xrx_sdi.xrxpll_yx_sdi.xlcvco_sdi_rx.xi18
Error: parameter "pwr" not found for instance
xtenbit_sdi_rx_topall.xtenbit_sdi_rx_top.xrx_sdi.xrxpll_yx_sdi.xlcvco_sdi_rx.xi18
Error: Netlist compilation failed!
pwr is a build-in function for hsim. Why it doesn't pass the compilation? Thanks
XI18 is a subcircuit as below. It is a varactor, PVAR12_CKT_RF.
XI18 P PUMP PVAR12_CKT_RF L=0.5U W=5U NF=4
Peter Chang