howto: modeling big chunks of memory

[umairsiddiqui]

sir, i require vhdl code, to model big chunks (not continuous) of RAM -- how to use
linkedlist for this purpose....please provide example code/paper???

 

[semiconductorman]

If you need only a functional model and not bother about timing , Then a linked list is defintely a viable option. How this is done is prety silmple you could write a C program for linked list and then use it as a PLI . If you need help in modelling in C there are 100s of sites available just search for tutor for linked list but while designing make sure of a few things like when memory is writen make sure that that praticular address is not there in your linked list already else u will have double entry for the same address .
If on the other hand u don't want to use PLI then u can still design it using verilog itself . make 2 arrays , 1 for storing address and other for storing data . when some thing is being written run through the address array to see if it is there , if you find it use the index of the match to retrive data from the data array . Give a little thought and u'll figure out what u need to do . If you want more details , u can send a message to me
-vikas

 

[sarath51]

if u verilog simulator support direct C interface then it a better , efficient way of intergarting C code