matrixofdynamism
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Netlist contains information on how the logic gates and flip flops are connected together, but we have so many different types of netlists when designing and simulating digital circuits.
We have post-synthesis netlist (also called post-map), post-fit netlist (after full compilation) and we also have timing netlist (in TimeQuest, it needs to be generated based on a model and also either post-synthesis or post-fit netlist).
How is each of these netlists different?
We have post-synthesis netlist (also called post-map), post-fit netlist (after full compilation) and we also have timing netlist (in TimeQuest, it needs to be generated based on a model and also either post-synthesis or post-fit netlist).
How is each of these netlists different?