How would I replicate this VHDL process into Verilog

LearningSoMuch · Dec 25, 2017

How would I replicate this VHDL process into Verilog?

Code:

begin
		inputa <= (others => '-');
		inputb <= (others => '-');
		outputa <= "-";

		if a = '1' then b := "1"; else b := "0"; end if;

then inputa, input b, and outputa is

Code:

signal inputa, inputb, outputa : unsigned(31 downto 0);

a is input std_logic
b is variable b : unsigned(0 downto 0);

TrickyDicky · Dec 26, 2017

rather simple:

Code Verilog - [expand]
1
b = a;

inputa, inputb and outputb do nothing.

Privacy & Transparency