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how would i generate negative voltage in cmos

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Junior Member level 2
Dec 2, 2005
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hi just wondering... how can i generate negative voltage in CMOS... lets say my vdd is 3.3 v and i need to generate a negative voltage lets say -2.5 volt. how would i do it? ?

I don't think it is possible to generate a -2.5 V at DC. If you could, you would be running your supply at 3.3+2.5 = 5.8V, right?

In addition to artem's post:

You can use charge pump, but remember about your substrate. If your substrate is p-type you have to apply to the substrate the most negative voltage, so body terminal of all NMOS transistors in your design should be connected to this pumped negative voltage.

Why not use differential circuits and this way you won't need a negative voltage?

the reason behind generating negative voltage....

I am designing a flash a/d converters and for that i need static reference of voltage so i desided to use pmos transistor to behave as a resistor.... i tried supplying few millivolts to gate voltages but didn't work ( the refrence voltages for 15 pmos transistor gave me the range (2.34 to 1.9) but when i set gate voltage to negative 2.5 volt, i get good range i mean perfect range (2.45 to 90mv). i accidentaly put negative 2.5 volt which is true for behaving the transistor in resistor mode....

so show me some easy way to generate negative voltage....

i tried charge pump but didn't work out...tell me with picture if u can... thankx

You shoud use the negative voltage pump,
And the 'substrate' of the negative voltage nmos passgate must conect to the negative voltage,but
this 'substate of the passgate' is not the whole chip's gnd substate,it is generated by the trip pwell overlaped by deep-nwell.

you can use a boost convertor, using a coil and an internal/external capacitor. The coil can be done integrated with actual technology.

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