majestic.eda
Newbie level 6
Hi all,
I have coded a parameterized module in verilog. In this module, one particular parameter configuration leads to an illegal port width which looks like this: reg [-1:0] my_data; and I was surprised to find that VCS didn't flag any error or warning for this. :shock: Functionally, the design is still working fine because in this particular configuration, signal my_data is left unconnected (is not connected anywhere in the module).
I doubt whether it will synthesize!! Any comment/help is welcome.. :smile:
I have coded a parameterized module in verilog. In this module, one particular parameter configuration leads to an illegal port width which looks like this: reg [-1:0] my_data; and I was surprised to find that VCS didn't flag any error or warning for this. :shock: Functionally, the design is still working fine because in this particular configuration, signal my_data is left unconnected (is not connected anywhere in the module).
I doubt whether it will synthesize!! Any comment/help is welcome.. :smile: