How to write self checking test bench for uart.v

[kalpana.aravind]

uart testbench

Hi everyone,

I am new to verilog Hardware Description Language.
I would like to know about writing test bench.
I need to write the a self checking test bench that fully exercises the Verilog UART module uart.v
The uart.v can be found at the following link.
https://www.asic-world.com/examples/verilog/uart.html
As I beginner I am just learning the verilog, so I have no idea how to proceed with this.
So please If any body is familiar with writing testbench code, please give me some suggestions.
It would be a great help if anyone, who has already written the code can email to me sample code.

Any suggestions welcome.

Thanks

 

[rakesh_aadhimoolam]

verilog testbench for uart

Hi...........

I'M quoting here a simple example..............


The name of the file is and1.v
-------------------------
module and1(a,b,c);

input [3:0]a,b;
output [3:0]c;

wire [3:0]a,b;
reg [3:0]c;

initial
begin

c = a & b;

end

endmodule

--------------------------

`include "and1.v"

module Tb();

reg [3:0]a,b;
wire [3:0]c;

and1 dut(a,b,c);

initial
begin
a <= 4'b1010;
b <= 4'b0111;
end

initial
begin
$display("%b",c)
end

endmodule

 

[mssajwan]

testbench for uart

hi,
if u r using some simple simulators...it will be good to display the messages.
you can instance the RTL in a module and apply the stimulus.
but if u rusing cadence or VCS then dump the waveforms. and check it.

 

[aji_vlsi]

self checking testbench example

Hi,
A "self checking" will mean you ddon't have to visually check outputs from log/dump file - it should do "SELF Check". In UART - what you send is what you receive at output, so data integrity check is fairly simple if you have the right abstraction level. You should add assertions to do the protocol checks.

Hi everyone,

I am new to verilog Hardware Description Language.
I would like to know about writing test bench.

We cover this in our CFV course. A course is about to be scheduled next week, see: www.noveldv.com and contact me at cvc.training <> gmail.com if interested.

I need to write the a self checking test bench that fully exercises the Verilog UART module uart.v
The uart.v can be found at the following link.
h**p://www.asic-world.com/examples/verilog/uart.html

So you get the design/RTL here.

As I beginner I am just learning the verilog, so I have no idea how to proceed with this.

If you really want to "learn" it - do it yourself with guidance. We show several kinds of testbench designs in our course and let you build the TB.

You may also choose to read books such as Writing TestBenches and learn it yourself.

It would be a great help if anyone, who has already written the code can email to me sample code.

Any suggestions welcome.

Thanks

My Humble Suggestion - please don't ask for the code - then how will you learn? You get RTL code off web, TB via email, then where will you learn?

Sorry if that hurts, but I would rather guide you in the correct direction than trying to be nice in email but in reality spoil your future - by giving you source code.

Ajeetha, CVC
www.noveldv.com