How to write parasitic file using Design Compiler for a hierarchical design

[gr_osu]

I want to do power calculation using PT_px and I am using Synopsys Design Compiler to generate parasitic file and .sdf file to be used by the Prime Time, but I am having so many errors when I read the paras tics and delay file. Main complaint is that it is not able to find related components in the hierarchical design. I saved the netlist using -hier option and as .ddc file in design compiler. Please help ..

 

[soloktanjung]

Hello,

Did you do like this?

change_names \
	-rules verilog \
	-hierarchy

write \
	-format verilog \
	-hierarchy

Please post the the errors you got in PrimeTime so that it is easier for other members to help.

Thank you.

Hairo

 

[gr_osu]

I am trying to do a vector free power calculations for different switching activity rates. The top entity has 6 components and then each component has at least 2 components inside it. I compiled the design using Synopsys DC. I have only two simple constraints ( creat_clock –period 5 [get_ports clk] and wire load model). I saved the netlist as [6port.ddc] a .ddc with –hier option [write -hierarchy -format ddc -output 6port.ddc ]. I saved parasitic [write_parasitics -out mapped/6portp ].

Then in pt_shell I do

1. set power_enable_analysis TRUE
2. set power_analysis_mode averaged
3. set search_path “ …”
4. set link_library “..”
5. read_ddc 6port.ddc
6. link

It is giving bunch of warnings like ...

Warning: Unable to resolve reference to 'swport_1' in 'controller'. (LNK-005)
Warning: Unable to resolve reference to 'swport_0' in 'controller'. (LNK-005)
Warning: Unable to resolve reference to 'swport_4' in 'controller'. (LNK-005)
Warning: Unable to resolve reference to 'swport_5' in 'controller'. (LNK-005)
Warning: Unable to resolve reference to 'swport_3' in 'controller'. (LNK-005)
Warning: Unable to resolve reference to 'swport_2' in 'controller'. (LNK-005)
Creating black box for port1/swport_1...
Creating black box for port2/swport_0...
Creating black box for port4/swport_4...
Creating black box for port3/swport_5...
Creating black box for port5/swport_3...
Creating black box for port6/swport_2...

Information: Removing 48 unneeded designs..... (LNK-034)

Warning: Module 'swport_1' in file 'mapped/6port.ddc' is not used in the current design . (LNK-039)
Warning: Module 'swport_0' in file 'mapped/6port.ddc' is not used in the current design . (LNK-039)

Then reading parasitic file it gives many errors of this nature …

Error: Could not resolve net 'port3/input_fifo/a1/n80'. (PARA-075)
Error: Could not resolve net 'port3/input_fifo/a1/n81'. (PARA-075)
Error: Could not resolve net 'port3/input_fifo/a1/n82'. (PARA-075)
Error: Could not resolve net 'port3/input_fifo/a1/n83'. (PARA-075)

I didn't do change names...please explain what it is. Also my files are in VHDL.

Please help .....

 

[gr_osu]

I have been waiting for some help...please any input will greatly help

 

[rk_learn]

Looks like your link_library setting is wrong. Use set link_library "*"

 

[soloktanjung]

Hi,

I don't understand why you use this command:

write -hierarchy -format ddc -output 6port.ddc

instead of this:

change_names \
	-rules verilog \
	-hierarchy

write \
	-format verilog \
	-hierarchy
	-output mynetlist.v

to generate the netlist from DC.

If you use the second method, you can read the netlist in PT using:

read_verilog mynetlist.v

 

[poluekt]

gr_osu, try this:

set search_path [list . your_search_path]
set link_path [list {*} your_db_files_for_standart_io_cells_and_ip ]  # default value link_path is *

read_ddc ${TOPLEVEL}.ddc     # or  read_verilog ${TOPLEVEL}.v
current_design $TOPLEVEL
link

hairo, you can use verilog netlist as well as ddc data base (netlist + design constraints).

 

[soloktanjung]

Thank you Poluekt.

Gr_osu, your search_path and link_path is not setting correctly. Probably the directory pointed to the link_path is not correct.