How to write a function in Verilog which takes a vector as input and outputs a vector

[avimit]

Can somebody suggest me how to write a function in verilog which takes a vector as input and produces a vector as output, and the function iteself is independent of the length or size of the vector. I need the syntax of the function.
In vhdl I can do it very eaisly
FUNCTION myabs(s1:std_logic_vector) return std_logic_vector is
--this function returns absolute of the input std_logic_vector
VARIABLE V : std_logic_vector(s1'high downto s1'low) ;
BEGIN
V := s1;
for i in V'low to V'high loop
V(i) := V(i) XOR V(V'HIGH);
end loop;
V:=V+V(V'HIGH);
return V;
end myabs; -- end function

Note that the function does not mention anywhere the 'size of' or the 'width of' the input or output vectors, instead, 'high and 'low vhdl attributes are used.
Can somebody write this in Verilog?

 

[xysafety]

verilog functions

In verilog, You can use alsto the function or the task to finish it .
It is very similar to the VHDL about the function.
I suggest you find a verilog language to refer, then you can get it soon

 

[echo47]

verilog built in functions

I don't think Verilog has anything like that. The best alternative I know is to pass a parameter (possibly named "length") to the Verilog module.

module top(in, out);
  parameter             length = 16;
  input    [length-1:0] in;
  output   [length-1:0] out;

  foo #(.length(length)) u1 (.in(in), .out(out));
endmodule

module foo(in, out);
  parameter             length = 0;
  input    [length-1:0] in;
  output   [length-1:0] out;

  assign out = in + 1;
endmodule

 

[avimit]

function verilog

Well echo47, thanks very much for your reply. But there are built in functions say for example '&&' which do not know the 'length' or 'size' or 'width' of vectors passed to them, yet the do the job. I wonder how they work?
kr,
Aviral Mittal

 

[echo47]

length function in verilog

The compiler knows the value internally, but the language authors simply didn't give us an operator to access it. Big oversight in my opinion. Imagine the C language without the sizeof operator. I think SystemVerilog provides the $bits function.

 

[sleary]

Very simple...

function [7:0] convert_nibble_to_char;
      input [3:0] data;
      begin
         convert_nibble_to_char = (data < 4'd10) ? 8'h30 + data : 8'h3f + data[2:0];
      end
   endfunction // convert_nibble_to_char