How to verify SigmaDelta desgin in Synthesizer

[youyang]

Hi All,

I have a MASH111 digital SDM coding in verilog. I am now confused about how to verify whether the SDM design is right or not. I mean the input (both integer and fraction parts) has so many possible patterns that I can't verify its function exhausively. Does someone have methodology on it?
Thinks

 

[fcfusion]

You can se if the output bitstream represents the input signal correctly. To do this you only need and adder and a register to implement a simple accumulator. Assuming you are using a 1-bit quantizer, all you have to do is something lke this:

reg [15:0] accumulator;

if (reset) accumulator=0;
else begin
if (quantizer_output==1) accumulator = accumulator +1;
else accumulator = accumulator -1;


The accumulator will work as a very simple low pass filter. If you apply a sinusoidal signal to the input, the accumulator's output will be a sinusoid as well. This is the way I do and it works very well for me. This method does not work with square or triangular waves, only sine waves.

Hope it helped