How to verify DFT patterns

[questionmark]

We implemented Scan Chain, BIST, Boundary Scan and some test modes for several IPs (such as PLL). We developed our own TAP controller and expand the JTAG instructions for BIST purpose.
My question is: How to verify various patterns of each test? I believe there should be some work in both RTL verification and Gate-level simulation.
To be more specific, which test need to develop verification environment by ourselves and which can generate testbench by tools.
Any one can help? Thanks.

 

[yp0716]

I don't have many experience, but I think the atpg tool can output the testbench which is verilog file.
It can be simulated with simuate tools. Am I right?

 

[newcpu]

For scan chain, you can run verification with modifying the verilog test bench from TertraMax. For BIST and JTAG, you can also use testbench from the related tools.

 

[yln2k2]

Hi ,

1) For Extended JTAG Instructions , You should Extend your JTAG Model such that
It will drive your own'n instructions and make sure RTL behaviour is correct and take the same to Gate Level simulations too .

2) BSD - I think Tools will generate Test bench , if you create your own BDS cell then you need to create TB based on your cell logic .

3) Scan Chain , I think ATPG tool from Mentor may be enough ?


regards
yln