how to verify clock domain crossing ?

[shastri.vs]

bus bridge verification

how to verify clock domain crossing ??
I have implemented a bus bridge using handshake mechanism.
can anybody tell tell me what are the methods to verify it.

 

[kujigaya]

i think the most straightforward way is through gate level simulation with SDF, where the clocks are sweeped/skewed with each other

the first stage of each double FF synchronizer is ignored for timing checks

 

[skyfaye]

You can also use CDC tools like Atrenta CDC Checker.

 

[shastri.vs]

kujigaya can you please explain a little more.
what kind of timing checks need to be performed.

 

[kujigaya]

during netlist simulation with SDF, all timing checks are enabled for all FFs except for the 1st FF of the synchronizer (VCS has this feature)

the goal is to check if the data bus crossing do not violate setup/hold timing (i.e. the synchronized control signal properly gates the data to the destination clock domain, and that the data does not change while the synchronized signal is asserted)

the test needs to be ran multiple times. each iteration has a different skew/shift between the 2 clocks