How to verify a netlist generated by synthesis tool.

[nikhilindia85]

hi guyz.i want in detail procedure of how to verify a netlist generated by synthesys tool.its urgent.i need help from u guyz

 

[vinodkumar]

Re: gatelevel simulation

hi,when we r doing synthesis we will get netlist,doing simulation or verification after synthesis called post synthesis simulation,all tools provide this option of doing simulation for netlist.

what is need is u should specify wht tools u r using.


bye.

 

[nikhilindia85]

gatelevel simulation

i am using cadence NCsim

 

[mssajwan]

gatelevel simulation

instead of your rtl instance the netlist.
use the same verification environment.

 

[yln2k2]

gatelevel simulation

Hi ,

Please take care of following ...

1) Libraries - zero delay simulation models ...
2) For synthesis netlist you can skip "specify" blocks ...
so check what option to skip the same ... for vcs/modelsim option is +nospecify
3) Top Level HDL need to replaced with netlist ..

if you need specific help ... let me know ...

regards
yln

 

[phoenixfeng]

gatelevel simulation

the file u need:
1 netlist file
2 sdf file
3 synthesized memory block if u use cell library in you design

 

[FLEXcertifydll]

gatelevel simulation

any industrial simulation tool U can employ

1. netlist
2. sdf file with the corner U care
3. simulation modules of layout library
4. if any hard core, simulation model also
5. any processor U used, need the simulation model
6. for ATPG simulation, perhaps U need the hard gate-level netlist, because not all simualtion model provide it.

 

[vinodkumar]

Re: gatelevel simulation

hi
may i know wht synthesis tool you r using becoz the procedure to do post synthesis simulation differs.if you r using build gate synth we have command write_sdf to write file which is required for post synthesis simulation,whereas if you r using RTL compiler we dont have commands to get sdf file and we need to go for another procedure to do in this case.

i mean you plz specify the wht synthesis tool u r using.

i hope this helps u if so plz dont forget to press help button.

bye

 

[shiv_emf]

gatelevel simulation

top module will be applying inputs to design under verifcation.. it can be either netlist or rtl code...

wht makes da diference.. !! test bench which ws used for Rtl verification can be used rite !

 

[Adam.Yakuvitz]

gatelevel simulation

Mr. nikhilindia85

I am not sure of all the responses that you are getting to your question.

After first level synthesis, there are two sorts of verification that needs to be done; functional and timing. Both verification can be done with static verification (ie. non-vector-based) tools.

Static Functional verification can be done with an Equivalency Checking tool like Cadence's Conformal-LEC and Static Timing Verification can be done with Synopsys PrimeTime product.

Dynamic Verification like running on a simulator are time prohbitive and you will have to write the testbench. Morevoer identifying an errors will also take a long time. Static tools like LEC and PrimeTime will allow quicker means to localizing functional or timing problems and without any testvectors.
--
ay

 

[nikhilindia85]

Re: gatelevel simulation

i am using RTL compiler for synth.how to verify the netlist with rtl testbench.in which tool we can do that?

 

[aji_vlsi]

Re: gatelevel simulation

i am using RTL compiler for synth.how to verify the netlist with rtl testbench.in which tool we can do that?

With same testbench, just provide the netlist as DUT and any simulator like NC, VCS, Modelsim can do the sim. However there are several issues related to signal naming, debug, coverage, speed of sim etc. I cover those issues as part of a Workshop on GLS (Gate Level Sim) soon to be announced in Bangalore. Contact us if interested.

Ajeetha, CVC
www.noveldv.com

 

[armardu]

gatelevel simulation

the file u need:
1 netlist file
2 sdf file
3 synthesized memory block if u use cell library in you design