how to verify 70% and 30% clock cycle

[carrot]

Hi -

Can anyone help me in telling, How do verify 70% on and 30% clock cycle ?

Thanks,
Carrot

 

[jbeniston]

In STA or simulation?

create_clock -waveform ...

 

[KlausST]

Hi,

You speak of duty cycle?

What PWM frequency?
What resolution?
Do you prefer a digital or an analog solution?

Klaus

 

[carrot]

Hi,

You speak of duty cycle?

What PWM frequency?
What resolution?
Do you prefer a digital or an analog solution?

Klaus

I want to test this in simulation. Digital solution.

 

[artmalik]

if you running spice sims....you can create a clock with 70% and 30% duty cycle and xor the two waveforms....
you will see spikes in the output waveform....

in STA, you will have do with edges of output....some .tcl script will need to be written...

 

[KlausST]

Hi,

if you running spice sims....you can create a clock with 70% and 30% duty cycle and xor the two waveforms....
you will see spikes in the output waveform....

The output waveform somehow not predictable.
Even when you synchronize the one clock to the other, then the output depends on phaseshift of both clocks.

But as long as the OP gives no further information it seems to me he is not interested in new answers...

Klaus