microtronics7
Junior Member level 1
Dear Sir,
I am simulating a multiplier in xilinx ise. I have written structural verilog code . Now i want to transfer the schematic to cadence. May I transfer it directly? I dont want to build schematic in cadence from scrap. Pls explain in detail since i am a novice.
Secondly, i want to find dynamic power using xpower. But it shows 0 dynamic power. I think i should use a clock to feed the inputs. How and where to use the clock. How to generate different inputs to compare my multiplier with others in dynamic power. Should i use dumpfile and dumpvars function?
Pls help!!!!
I am simulating a multiplier in xilinx ise. I have written structural verilog code . Now i want to transfer the schematic to cadence. May I transfer it directly? I dont want to build schematic in cadence from scrap. Pls explain in detail since i am a novice.
Secondly, i want to find dynamic power using xpower. But it shows 0 dynamic power. I think i should use a clock to feed the inputs. How and where to use the clock. How to generate different inputs to compare my multiplier with others in dynamic power. Should i use dumpfile and dumpvars function?
Pls help!!!!
