HOW to use virtuoso to generate verilog netlist from schemat

[altra]

cdl to verilog

HOW to use virtuoso to generate verilog netlist from schematic?
I know virtuoso composer can generate edf netlist ,cdl netlist ,but I don't know how to generate verilog netlist .
Does anyone know it?

 

[cdncrk]

edif2verilog

HOW to use virtuoso to generate verilog netlist from schematic?
I know virtuoso composer can generate edf netlist ,cdl netlist ,but I don't know how to generate verilog netlist .
Does anyone know it?

it can't

 

[seasonyangd]

virtuoso verilog netlist

NOt virtuoso, should be composer!!

 

[khorram]

virtuoso netlist

You can generate EDIF and then use edif2verilog convertors to have a verilog netlist. Cadence package includes lots of convertors.

Regards,
KH

 

[altra]

virtuoso verilog

do you mean that virtuoso have the edif2verilog feature .where can I find it.
or other software has the ablity.
---------thanks a lot for you help