how to use VHDL Timing verfication between two signal

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Thanx trickydicky and xtcx for this great dicussion on this topic. i had learn some new things and this discussion has provide me a nice insight of VHDL timing verfication which i was looking for..
 

Anyway I'm stuck at some point in RTL itself, I shall re-open the thread when I exactly come to that simulation and timing. Thanks for your support tricky
 

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