Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

How to use Verilog UDP in other modules?

Status
Not open for further replies.

skamthey

Member level 3
Joined
Jan 28, 2009
Messages
54
Helped
7
Reputation
14
Reaction score
7
Trophy points
1,288
Activity points
1,647
Hi,
I want to use an UDP say "primitive.v" in any other module.
How can i do this.
I just add that primitive.v file into existing module file, and make instantiation but it's not working.
 

verilog udp primitive

skamthey said:
Hi,
I want to use an UDP say "primitive.v" in any other module.
How can i do this.
I just add that primitive.v file into existing module file, and make instantiation but it's not working.

Show us exact code and the error you are getting to receive better help.

Ajeetha
Next SV course starting in Feb 09 end. See:
https://sv-verif.blogspot.com for details
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top