How to use variable in generate loop

[ismailov-e]

Hi everybody!
Can anybody help me to understand how to use variable outside of generate-endgenerate loop.
I found some explanation. For example:

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Code Verilog - [expand]
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generate
for(i=0; i<SIZE; i=i+1)
begin:addbit
wire n1,n2,n3; //internal nets
xor g1 (n1 ,a[i] ,b[i]);
xor g2 (sum[i] ,n1 ,c[i]);
and g3 (n2 ,a[i] ,b[i]);
and g4 (n3 ,n1 ,c[i]);
or g5 (c[i+1] ,n2 ,n3);
end
endgenerate

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In the preceding example, each generated net will have a unique name, and each generated
primitive instance will have a unique instance name. The name comprises the name of the block
within the for-loop, plus the value of the genvar variable used as the loop index. The names of
the generated n1 nets are:
addbit[0].n1
addbit[1].n1
addbit[2].n1
addbit[3].n1

I can't use for example prereg <= addbit[0].n1.
How can i use instance outside generate loop?
The relative generation i saw in bram generation in AXI4-Full.
But the register have the same name but multiplied.

 

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n1 is local to the for loop if you want to use it both inside and outside the loop then you should make it local to the module, this is similar to software variable scoping rules.

 

[dave_59]

But you can refer to prereg <= addbit[0].n1; outside of the generate block. But what you cannot do is refer to addbit[j],n1 where j is a variable. That is because addbit is not an array; it is a block scope. The generate loop creates a unique scope name for each iteration of the loop and appends [NN] to the block name. Because of conditional generates and defparam statements, the contents of each block can be different - unlike a regular array where each element has an identical type.