how to use useful skew well~

[sophiefans]

Hello every one,

For one certain design, data path almost has no margin, so i have to fix setup violation by useful skew. So i check slack margin before/after violation path and set_clock_tree_exception on clock pin.
While the result is, some violation was fixed by early/delay clock pin, but some new violations appear. So i am confusing , how i can fix violation by useful skew and don't cause new violations?




Thanks,
Sphiefans

 

[matter]

You cannot always fix all violations using useful skew. Useful skew can be used only when you have enough slack on next/previous stages. Without slack values and how much clock tree exception was set, its hard to figure out the issue, but my guess is that you probably went overboard with 'useful skew' which in turn lead the to new violation. Another thing to take into account is the existing clock tree skew. So along with slack values, take the overall clock tree skew also into account while trying to adjust the insertion delays using useful skew.

 

[sophiefans]

Hi matter,

Thanks for your reply, the global useful skew should be considered too. And another question, what 's your method to fix a design which data path is almost reasonable and with no margin? Except for useful skew , what else?

You cannot always fix all violations using useful skew. Useful skew can be used only when you have enough slack on next/previous stages. Without slack values and how much clock tree exception was set, its hard to figure out the issue, but my guess is that you probably went overboard with 'useful skew' which in turn lead the to new violation. Another thing to take into account is the existing clock tree skew. So along with slack values, take the overall clock tree skew also into account while trying to adjust the insertion delays using useful skew.

 

[matter]

Useful skew will be pretty much my last resort. Since you have mentioned the data path is 'almost reasonable' and you still have timing closure issues, this basically implies that your design is broken. I would go back to the logic designers to see if they can rip out some logic or add a new flop stage.

If you data path looks good and overall clock skew also looks good, there isn't really much we can do. I am assuming that you have already checked to make sure that the transitions are crisp and xtalk is minimum, ensured good placement, checked if high drive and low vt cells can be swapped in and so on...

 

[sophiefans]

Hi Matter, Thanks for your reply, i got some useful idea form you words.

Useful skew will be pretty much my last resort. Since you have mentioned the data path is 'almost reasonable' and you still have timing closure issues, this basically implies that your design is broken. I would go back to the logic designers to see if they can rip out some logic or add a new flop stage.

If you data path looks good and overall clock skew also looks good, there isn't really much we can do. I am assuming that you have already checked to make sure that the transitions are crisp and xtalk is minimum, ensured good placement, checked if high drive and low vt cells can be swapped in and so on...