NickDefick
Newbie level 1
Hi,
I am new to vhdl, I would like to modify this code to simulate 4 led's that the following:
0 = on
x = off
clock 1: 0000
clock 2: 000x
clock 3: 00xx
clock 4: 0xxx
clock 5: xxxx
clock 6: xxx0
clock 7: xx00
clock 8: x000
clock 9: loops the code back to what clock 1 is like.
This is what I have so far as far as code:
any help would be great, maybe someone here could point me in the right direction.
I am new to vhdl, I would like to modify this code to simulate 4 led's that the following:
0 = on
x = off
clock 1: 0000
clock 2: 000x
clock 3: 00xx
clock 4: 0xxx
clock 5: xxxx
clock 6: xxx0
clock 7: xx00
clock 8: x000
clock 9: loops the code back to what clock 1 is like.
This is what I have so far as far as code:
Code:
library IEEE;
use IEEE.std_logic_1164.all;
entity state_T is
port(
clock : in std_logic;
reset : in std_logic;
o : out std_logic_vector(2 downto 0)
);
end state_T;
architecture arch of state_T is
component T_ff
port (
clk : in std_logic;
clear : in std_logic;
T : in std_logic;
Q : out std_logic;
Qbar : out std_logic
);
end component;
signal T3, T2, T1, T0, Q3, Q2, Q1, Q0, Q3bar, Q2bar, Q1bar, Q0bar: std_logic;
begin
s3 : T_ff port map (
clk => clock,
clear => reset,
T => T3,
Q => Q3,
Qbar => Q3bar
);
s2 : T_ff port map (
clk => clock,
clear => reset,
T => T2,
Q => Q2,
Qbar => Q2bar
);
s1 : T_ff port map (
clk => clock,
clear => reset,
T => T1,
Q => Q1,
Qbar => Q1bar
);
s0 : T_ff port map (
clk => clock,
clear => reset,
T => T0,
Q => Q0,
Qbar => Q0bar
);
T3 <= (Q3bar and Q2) or (Q3 and Q2bar);
T2 <= (Q2bar and Q1) or (Q2 and Q1bar);
T1 <= (Q1bar and Q0) or (Q1 and Q0bar);
T0 <= (Q2bar and Q0bar) or (Q2 and Q0);
O(3) <= Q3;
O(2) <= Q2;
O(1) <= Q1;
O(0) <= Q0;
end arch;any help would be great, maybe someone here could point me in the right direction.