how to use % operator in verilog

[taolibuyan]

verilog modulo operator

I got this error "Operator % is only supported when the second operand is a power of 2." My second operand is a integer constant. Is it synthesizable? I have to use this operator.

 

[rberek]

modulo operator verilog

What tool is giving you this error? How are you using the modulus operator?

 

[echo47]

verilog modulus operator %

Many synthesis tools don't support integer division/modulus/remainder unless the calculation is trivial, such as division by a power of two. If your value isn't a power of two, then you are probably out of luck.

Maybe you can use another approach such as building your own math module, or using a math core from your software's IP library.

Or maybe you can approximate the division by multiplying by the fraction 1/K instead of dividing by K.

If both operands are small, you could fetch the result from a ROM lookup table.

 

[taolibuyan]

verilog mod operator

Xilinx ISE 8.1

My codes are simply

if (A % B > ***)
....................

What tool is giving you this error? How are you using the modulus operator?

Added after 5 minutes:

Thanks. It seems it's impossible to use modulus/division operators.

The range of my operands is too large for a lookup table. I will try math core.

Many synthesis tools don't support integer division/modulus/remainder unless the calculation is trivial, such as division by a power of two. If your value isn't a power of two, then you are probably out of luck.

Maybe you can use another approach such as building your own math module, or using a math core from your software's IP library.

Or maybe you can approximate the division by multiplying by the fraction 1/K instead of dividing by K.

If both operands are small, you could fetch the result from a ROM lookup table.

 

[gsuresh418]

Re: modulo operator verilog

What tool is giving you this error? How are you using the modulus operator?

Iam using xilinx 9.1 version

 

[yanzixuan]

Re: verilog modulo operator

It's not synthesizable is your second operand is not 2.
you need design by hand.

 

[gsuresh418]

ok.. TaQ very much..for ur help

 

[malikkhaled]

Re: modulo operator verilog

Hi, i want to make a verilog module that calculates (A mod B) where b is 31, the result remains between 0 to 31 whatever the input A is,,, any help in this regard would be appreciated.. i am using xilinix ise 14.1..

 

[ads_ee]

Re: modulo operator verilog

Hi, i want to make a verilog module that calculates (A mod B) where b is 31, the result remains between 0 to 31 whatever the input A is,,, any help in this regard would be appreciated.. i am using xilinix ise 14.1..

Shouldn't this be A mod 32? Which the results will lie in the 0 to 31 range? If so this should be synthesizable.

-alan

 

[upadrastapavan]

If you are not worried of accuracy you can do the modulo operation in verilog synthesizable by following math operation

x mod k

1.Calculate 1/k and then multiple with a number which is in power of two like 32,64,256.....
2.Multiply the resultant value with x and then divide by the power of 2 number that is been used for division

 

[axcdd]

There is bug in xilinx tool

Modulo will be synthesizable when (x mod k) -> x is signal not variable.
ofc k dont need to be the power of 2. Somehow synthesis tool requires k to be power of 2 when x is variable.

You can check it in some paper -> xilinx design recommendation or sth. The recommandation for counters to MAX_VALUE value is
cnt <= (cnt+1) mod MAX_VALUE

 

[TrickyDicky]

There is bug in xilinx tool

Modulo will be synthesizable when (x mod k) -> x is signal not variable.
ofc k dont need to be the power of 2. Somehow synthesis tool requires k to be power of 2 when x is variable.

Thats understandable - its preventing the generating of the massive logic required for the mod operation.
Basically, the mod or % operator is pretty useless in synthesisable HDL, as the fmax would be rather slow.

 

[axcdd]

When K is constant xilinx sythesis handle is very well with resourses usage twice less then altera and very good fmax. But in Altera, quartus uses lmp_div cores and u get sloppy design. So i stopped using modulos after all, because all in all imho quartus is far better enviroment (maybe except modulo implementation)