A device's "rating" has many facets, if you drill down into the
details. The foundry will call it out at its lowest limiting aspect.
It's quite likely that a FET has a higher Vgs and Vgd than its
long term reliable Vds at worst case HCI bias. So sometimes
(in some topologies) you can safely use a device beyond its
simple scare-the-innocent rating.
If you are using an SOI technology you can take advantage
of the infinite (for practical purposes) body-to-substrate,
hence body-body, voltage and use cascoding techniques to
divide the applied "off" voltage into bite-sized Vds portions.
The problem you run into, quickly (N>2) is that the higher
gates now require their own, and well phased, high-swing
gate drivers, and the elaborateness snowballs.
Or, you could use the "I/O" thick oxide transistors, which
might be capable as is. Or find a flow where this is true.
For small amounts of circuitry you may be better off with
an internal LDO and level shifting at the ins and outs.