How to use hard IP timings information in top module timing constraints

[javi]

Hi,

I have an hard IP ( in Netlist form) with the timing information setup/hold to clock , clock to output delay , pad to pad delay and the maximum operating frequency. The given information looks likes a data-sheet report or say overall IP interface timing budget.

Now , when I integrate it into my top module with dont_touch options , how do I specify my top module clock timing constraints while taking considerations of the hard IP timings.

1. How to consider the setup_clock timing information of the IP. Will it affect the top module clock period specification? .
2. Similarly which portion (AT or RT ) of the top module timing analysis is affected by the clock to output delay of the IP.

I hope this is common flow query irrespective of the tools being used.
Is their any good document for any ASIC flow specifies IP FLOW integration / Timing constraints aspects.

Thanks,
Javi

 

[feel_on_on]

I think :

hard ip will communication with other module ,and if the same clock domain, you will check
the timing in the clock period constraint .

 

[lostinxlation]

Standard cells are hard IPs. flops have setup/hold time, combinatorial std cells have input to output delay. Hard IPs are nothing different from those std cells in the design flow and you can treat them as large std cells.

 

[dftrtl]

You need read .libs for IP's