How to use global parameters in System verilog

[KillaKem]

I have modules that define a parameter N, I also have an encapsulating module that instantiates all the other modules and it also defines the parameter N, so the problem I'm having is that every time I want to change the value of N I have to go into all the modules one by one and change N's value, I then have to change the value of N in the encapsulating module too, is there any way I can I define the parameter N such that when I only have to define it once and the value gets used by all the modules? Sort of like global variables in high level languages like Java, C++.

 

[ads_ee]

Sort of like global variables in high level languages like Java, C++.

Hmmm, I thought that using OOP and global variables in the same sentence was forbidden.

Well I would suggest not using something global like `define. It becomes a problem with maintainability when you have more than one person working on RTL and they end up working on the same design in different modules. e.g. P1 works on modules A, C, and E and declares `define WIDTH 16 in module A and uses `WIDTH in all three of his modules (A, C, and E). P2 works on modules B & D and declares `define WIDTH 32 in module B and uses his `WIDTH in both B & D. Oops, the top level file where we have instantiated modules A, B, C, D, and E in order doesn't synthesize or compile correctly.

Instead use a parameter and pass it between the module hierarchy.

For example:

---

Code Verilog - [expand]
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//-------------------------------------------------------
// top level module instantiate modules A & B
module TOP #(
  parameter pW = 16
) (
  output  [pW-1:0]  OUT,
  input    [pW-1:0]  IN
);
wire [pW-1:0]  a_to_b;
 
// instance A
A  #(
  .pWIDTH  (pW)
) A_inst (
  .OUT  (a_to_b),
  .IN     (IN)
);
// instance B
B  #(
  .pWIDTH  (pW)
) B_inst (
  .OUT  (OUT),
  .IN     (a_to_b)
);
endmodule
 
//-------------------------------------------------------
// module A
module A #( 
  // Module Parameter(s):-----------------------------
  parameter  pWIDTH = 4   // number of bits
) (
  // I/O declarations:---------------------------------
  output  [pWIDTH:1]      OUT,   // - signal(s) output
  input    [pWIDTH:1]      IN      // - signal(s) input
);
// the module code
endmodule
 
//-------------------------------------------------------
// module B
module B #(
  parameter  pWIDTH = 4
) (
  output [pWIDTH-1:0]  OUT,
  input   [pWIDTH-1:0]  IN
);
// module code
endmodule

---

Now pWIDTH can be changed at either the TB level above TOP or by changing the pWIDTH declaration in TOP, without having to change all the other files.

Regards,
-alan