How to use generic modules in xilinx schematic editor

[eladin]

Dear every one,

I am working on a project using verilog and xilinx ISE.

I want to use as many generic modules as I can to ease the work (am i thinking correctly? is it better to work with generic?), and I Want to use the generic modules I make in the schematic editor, but I dont know how to change the generic parameter for different modules. e.g.
------------------------------------------------

this is a 2 to 1 mux, N bits wide, N being 8 by default


module Mux_2_to_1_N8bits #(parameter N=8)(
input [7:0] input_1,
input [7:0] input_2,
input select,
output reg [7:0] output_1
);

always @(*)
begin

if (select == 0)
output_1 <= input_1;
else
output_1 <= input_2;
end


endmodule



now what I want to be able to do, is create several instances of this mux in the schematic editor, but with different values of N, how do i do that?

Thank you

 

[eladin]

is this question like really stupid/answer is really obvious or doesn't any body know?

 

[TrickyDicky]

Its the weekend. Some people dont check the board.
Also, most people dont use the schematic editor (like me) as you cannot simulate the output and its not very portable, so most people (and thats is pretty much everyone in industry) use HDL for all levels. They also wouldnt create a single mux and instantiate it a load of times, they would just infer the mux inside code - but I appreciate you are probably a beginners and trying things out.

So, I would suggest not getting too hung up on the schematic editor, as it wont serve you for very long.

 

[mrflibble]

Also, most people dont use the schematic editor (like me) as you cannot simulate the output and its not very portable, so most people (and thats is pretty much everyone in industry) use HDL for all level.

Pretty much this. I have played with schematic editor in the past to see what's it all about, but I've never had a need to figure out how to parameterize it.

So lets turn this one around ... what is your motivation to use schematic editor as opposed to verilog/vhdl?

 

[eladin]

I am very thankful for the answers

So lets turn this one around ... what is your motivation to use schematic editor as opposed to verilog/vhdl?

I used the schematic editor to connect modules made up of 16 PE 15 DFF and 16 Muxes, so I thought it would be easier to connect with a gui instead of verilog,but from your responses, it seems its better to use verilog for that,why though?

In verilog I should do it by creating instances of modules and connecting them with wires correct ? is this not more complex than using the schematic editor ? I understand that using verilog would be better in terms of portability, but isnt it harder too ?

Also

as you cannot simulate the output

What do you mean exactly?

 

[TrickyDicky]

In verilog I should do it by creating instances of modules and connecting them with wires correct ? is this not more complex than using the schematic editor ? I understand that using verilog would be better in terms of portability, but isnt it harder too ?

Not really. HDLs are a lot more configurable and allow you to do paramaterised connectivity, that schematics will not let you do. Some people like looking at the schematics, but have to get over this when they realise they cannot parameterise it, cant simulate it and cant take it to another vendor.

What do you mean exactly?

You cannot run a schematic file through a simulator like Modelsim, and I doubt it will work in the ISE simulator without converting it to an HDL - and that means you end up with two copies of the same thing.

Moral of the story - forget about schematic entry tools for HDL (unless it's HDL designer, but that can be a bit of a pain too - but its expensive but no where near as bad as tool schematics.)

 

[eladin]

Well, thanks for all the info, ill shift to HDL only starting now

 

[mrflibble]

A wise decision.