How to use differential IOs as a single ended IOs in SPARTAN-3A FPGA kit

[hallovipin]

HI friends,

I am utilizing SPARTAN-3A FPGA board to connect 12 bit ADC to FPGA. I want to use RX expansion connector, which has 6 differential IOs. I want to use these 6 differential IOs 12 single ended IOs. Do I have to adopt a special methodology or what.
Also 40 IOs on the board are accessible through 100 pin FX2 (Herose) connector and I am not able to find a socket for it which fits into this connector. can u advise some way out.

 

[FvM]

I want to use these 6 differential IOs 12 single ended IOs.

Read the board user guide or a Xilinx Spartan 3A data sheet. The differential IO capability isn't but a supplementary option of certain I/O pin pairs. They can always be used single ended.

I am not able to find a socket

Check Hirose.com to learn about available connector types. Options are female board-to-board and IDC cable (1/40 ") connector. Enter "Hirose FX2" at your favourite catalog distributors and you'll hopefully get some results.

 

[hallovipin]

Read the board user guide or a Xilinx Spartan 3A data sheet. The differential IO capability isn't but a supplementary option of certain I/O pin pairs. They can always be used single ended.

@ Fvm
as always u r there to rescue. Thanx
When I made use of differential IOs as single ended IOs, ADC data didnt appear at the output pins. At the same time when I used IOs which are specifically single ended,
I didnt face any problem. But the problem is I had only 8 single ended IO at the board while I need 16.

Check Hirose.com to learn about available connector types. Options are female board-to-board and IDC cable (1/40 ") connector. Enter "Hirose FX2" at your favourite catalog distributors and you'll hopefully get some results.

In india we have either farnell or rscomponents, but both of them do not have FX2 female connector available.

 

[FvM]

both of them do not have FX2 female connector available

Yes, I know. Digikey e.g. has. I would also expect the vendor of the DevKits to supply the expansion headers. But I'm not using Xilinx and not familiar with their distribution channels.

 

[hallovipin]

any comment on differential and single ended IO query (asked in the previous post of mine).

 

[FvM]

any comment on differential and single ended IO query (asked in the previous post of mine).

review my previous answer

They can always be used single ended.

 

[hallovipin]

When I made use of differential IOs as single ended IOs, ADC data didnt appear at the output pins. At the same time when I used IOs which are specifically single ended,
I didnt face any problem.

 

[shitansh]

LVDS IOs are slow so perhaps you can not use LVDS IOs as single ended IO.

 

[FvM]

LVDS IOs are slow

They are among the fastest IO standards, the FPGA has.

When I made use of differential IOs as single ended IOs, ADC data didnt appear at the output pins.

I don't work with Xilinx, so I can't guess what you exactly did wrong in pin configuration. But Xilinx, as well as other vendors, has the option to operate any IO single ended. It's also clear from the DevKit description, that the extension connector offers 43 IO pins, none of them particularly restricted.