Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

how to use DesignWare cells?

Status
Not open for further replies.

quan228228

Full Member level 4
Joined
Mar 23, 2006
Messages
196
Helped
16
Reputation
32
Reaction score
3
Trophy points
1,298
Activity points
2,571
In my design, there are 2 places using DW02_mult. DW02_mult is multiplier of DesignWare. The synthesis result is that the area of these two DW02_mult cell is different.

I want to know why the areas is different. how does Design Compiler select the cell from DesignWare. Or Can i designate which cell to be used?


Thanks!
 

waynejwd

Newbie level 3
Joined
Aug 23, 2007
Messages
3
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,300
U just need to do 2 steps. 1st, include the designware lib when do lib setup. 2nd, instantiate the designware directly, just as "DW02_mult Inst_DW02_mult (ports)".

Best rgds,
Wayne
 

avimit

Banned
Joined
Nov 16, 2005
Messages
413
Helped
91
Reputation
182
Reaction score
23
Trophy points
1,298
Location
Fleet, UK
Activity points
0
The area may be differnet, because each instantiation of the mult may lie under different set of constraints. Say for example, one lies in the critical path, then synopsys will optimize it for timing, increasing its area, while the other if we assume, is in a relaxed timing path, will be optimized for area by synopsys. So each instance of the same DW component can have different area.
Synopsys selects DW components, mostly when you use operators, or when you explicitly instantiate in your design.
you can also hand instantiate them in your design. They are usually found in
$SYNOPSYS/dw
Hope it helps,
kr,
Avi
https://www.vlsiip.com
 
  • Like
Reactions: njr@1

    quan228228

    Points: 2
    Helpful Answer Positive Rating

    njr@1

    Points: 2
    Helpful Answer Positive Rating

quan228228

Full Member level 4
Joined
Mar 23, 2006
Messages
196
Helped
16
Reputation
32
Reaction score
3
Trophy points
1,298
Activity points
2,571
avimit said:
The area may be differnet, because each instantiation of the mult may lie under different set of constraints. Say for example, one lies in the critical path, then synopsys will optimize it for timing, increasing its area, while the other if we assume, is in a relaxed timing path, will be optimized for area by synopsys. So each instance of the same DW component can have different area.
Synopsys selects DW components, mostly when you use operators, or when you explicitly instantiate in your design.
you can also hand instantiate them in your design. They are usually found in
$SYNOPSYS/dw
Hope it helps,
kr,
Avi
https://www.vlsiip.com


yeh, you are right. These two places have different timing and driving capacity, so lead to different areas. I enhance the driving capacity by command "set load", the two area are almost equal.

thanks!

david
 

ivlsi

Advanced Member level 3
Joined
Feb 17, 2012
Messages
887
Helped
17
Reputation
32
Reaction score
16
Trophy points
1,298
Activity points
6,861
What's purpose of using the DesignWare modules? When their usage is recommended? When is not recommended? Thank you!
 

ivlsi

Advanced Member level 3
Joined
Feb 17, 2012
Messages
887
Helped
17
Reputation
32
Reaction score
16
Trophy points
1,298
Activity points
6,861
Isn't the DesignWare a cell (even complex, but still cell)? Is this a soft macro?

How fabs deal with DesignWare? It seems DesignWare's are not included in the STD libraries... Do fabs prepare special libraries for DesignWare's from Synopsys?

Do Cadence tools have the similar elements like DesignWare? How are they named there?

What's purpose of the DesignWare? Why are they needed?

Thank you!
 

englishdogg

Full Member level 5
Joined
Jan 10, 2012
Messages
250
Helped
38
Reputation
76
Reaction score
39
Trophy points
1,308
Location
India
Activity points
2,742
DesignWare - i would say more better known as components rather cell.
These are technology inependent and best optimized code for a specific implementation for e.g DW_mult most commonly used that i have seen

It is a multiplier overall and these are not foundry specific and hence not in the library but with the tool installation
Cadence have similar known as ChipWare Components

As i said purpose is to use the most optimized code for the a specific datapath implementation.
 

ivlsi

Advanced Member level 3
Joined
Feb 17, 2012
Messages
887
Helped
17
Reputation
32
Reaction score
16
Trophy points
1,298
Activity points
6,861
DesignWare ... not in the library but with the tool installation
So, is it implemented using standard cells (STD Cells) of the vendor/fab/foundry?
Some our vendor asked not to use DesignWare's because they did not prepared such cells in their libs...
 

englishdogg

Full Member level 5
Joined
Jan 10, 2012
Messages
250
Helped
38
Reputation
76
Reaction score
39
Trophy points
1,308
Location
India
Activity points
2,742
Using standard cells - yes
I would say that is strange since these are technology independent - di dyou witness any issues which you were using the product of this so called vendor

Probabaly they may have a different flow
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top