How to use chipscope in hierarchical design?

[tariq786]

I want to observe signals deep in my hierarchical design. For example lets say my design hierarchy is


Top Level
Module A
Module B
Module C
Module D


I am able to see signals at the top level using ICON and ILA cores that i have instantiated at the top level. But how to observe signals in Module D ?

I instantiated new ICON and ILA for module D, but Chipscope only shows ICON and ILA cores for the Top Level module.

I have also tried to add another control port to ICON core at the Top level and connect it to ILA in module D. But i get errors in the translation phase telling me that control port can not be active and tristate at the same time. Control port is declared as wire in the Top Level module and as inout in the Module D.

Please help

 

[rberek]

You have to rewrite your lower level modules to bring the desired signals up to the top level. At least that is the only way I've ever been successful at doing it.

r.b.