Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

How to use Cadence Tools to simulate PLL Phase noise

Status
Not open for further replies.
Z

zhancangF117

Newbie level 6
Joined
Feb 18, 2006
Messages
14
Helped
2
Reputation
4
Reaction score
1
Trophy points
1,283
Location
Beijing
Activity points
1,381
Hello, everybody
I want to simulate a PLL design's phase noise, could anyone help me, or offer some reference?
Thanks a lot!
 

use SpetreRF by selecting pss pnoise
 

Hi yaxazaa,

is that marketing or did you simulate a complete PLL with sucessful? I am very interessted in the capabilities of spectreRF to do that thing.

The problem I have is that a simple transient simulation of the first settling phase takes some hours. So pss-analysis need an already steady-state situation.

What are your tricks?
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top