using rams blocks spartan 3
ISE provides several ways of putting a Block RAM into a Xilinx FPGA.
You can infer the RAM with HDL code by using a large register array. Be sure to write your HDL in the recommended way. If you are using ISE's XST synthesis tool, see the ISE "XST User Guide" chapter "HDL Coding Techniques".
You can instantiate the block RAM primitive directly into your HDL. See the ISE "Library Guide" for your particular FPGA type, and then look for design elements having names such as RAMB16_S18_S18. This is a reliable technique but it is somewhat tedious because there are many ports to connect.
You can use ISE's CORE Generator (coregen) to build a memory module to your specifications. After you launch coregen, look for the "Memories & Storage Elements" section, and click something under "RAMs and ROMs". Then you can read the core's data sheet to see if it's appropriate for you needs.