how to use 2's complement arihmetic in Verliog?

[H.Hachem]

Hi,
I am looking for a way to force verilog to use 2's complement arithmetic. I'm not sure if it does it automatically. I heard somewhere that declaring the inputs as 'signed' would do the job. Can someone help me out?

 

[kingslayer]

As far as I know, Verilog 2001 has built-in support for this, just using signed nets and variables!

Cheers

 

[H.Hachem]

true. I tested it and you are right. The thing that puzzles me though, if I can declare inputs as unsigned in the module but signed in the testbench, or if I have to declare them as signed inputs in both.