Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronic Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

How to understand the Verilog A model of OSC in rflib, candence's library?

fjiang

Newbie
Joined
Jan 4, 2021
Messages
1
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
10
The source code is as follows:
1.png2.png

  • In the red box, why differentiate the noise voltage?
  • “vc = sqrt(2)* V(int)/amp ” should how to understand?
  • In my opinion,in the case of small vc, this can be converted into phase noise. 3.png
  • But I have some questions about the above two sentences,please help me.
 

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top