how to turn on mismatchflag=1 in Cadence with TSMC

[guow06]

From TSMC manual, I find this "The designers will need to turn off (mismatchflag=0) or turn on (mismatchflag=1) in the macro model for nominal or Monte-Carlo analysis". Any idea, how can I turn it on?

 

[erikl]

Don't know which version you're running. Formerly, it worked like this: View attachment Cadence_Monte_Carlo_simulation_tutorial_p15.pdf

 

[stud.taneja]

you can also make the sigma multiplier of your mismatch process equal to zero

 

[guow06]

I tried that and there was no mismatch. That's why I wonder if there is an option to turn on the mismatch in the design kits. I'm using tsmc90nm.

Don't know which version you're running. Formerly, it worked like this: View attachment 76254

 

[guow06]

I find the following from design kits doc, however I do not under what does it mean.

Marco MOS device usage:

3) MOS with mismatch effect:
Please enable the item "With Mismatch Effect" in CDF form of macro MOS devices. It will
generate the parameter "mismatchflag=1" in the netlist, and the "multi" parameter will
be generated according to the "fingers" item in CDF form. Then mismatch effect
is considered in simulation. Please note that current model does not support mismatch effect
for native devices.

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mismatchflag=1 or 0 should be set during the installation of the design kits. Right now in my design kits, all mismatchflag equals 0.
so unless I reinstall the kits, there will be no mismatch or process variation in the menta carlo simulation. Is that all correct? I have used IBM kits and had no problem with menta carlo simulation.