How to Translate from Verilog to VHDL

zwill12 · Oct 28, 2015

Code Verilog - [expand]
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assign Zero = (ALUOut==0); //Zero is true if  ALUOut is 0
always @(ALUctl, A, B) begin //reevaluate if these change
case (ALUctl)
0: ALUOut <= A & B;
1: ALUOut <= A | B;
2: ALUOut <= A + B;
6: ALUOut <= A - B;
7: ALUOut <= A < B ? 1 : 0;
12: ALUOut <= ~(A | B); // result is nor
default: ALUOut <= 0;
endcase
end

ads-ee · Oct 28, 2015

Code VHDL - [expand]
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Zero <= '1' when (ALUOut = 0) else '0';
 
process (ALUctl, A, B)
begin
  case ALUctl is
    when 0 => ALUOut <= A AND B;
    ....
    when others => ALUOut <= '0';
  end case;
end process;

Though you'll likely need some type conversions depending on how everything is defined.

How to Translate from Verilog to VHDL

zwill12

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zwill12

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Code VHDL - [expand]
1 2 3 4 5 6 7 8 9 10	Zero <= '1' when (ALUOut = 0) else '0'; process (ALUctl, A, B) begin case ALUctl is when 0 => ALUOut <= A AND B; .... when others => ALUOut <= '0'; end case; end process;

How to Translate from Verilog to VHDL

zwill12

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