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# how to transfer these pulses safely from clock1 to clock2

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#### sun_ray

Pulses are coming from a domain with 200 Mhz clock1 to a domain of 50 Mhz clock2 where clock1 and clock2 are asynchronous to each other. Now two such consecutive pulses can have minimum two clock cycles of clock1 gap and maximum eight clock cycles of clock1 gap.
What will be the digital logic that can safely transfer these pulses from clock1 to clock2?

pulses are coming from a domain with 200 mhz clock1 to a domain of 50 mhz clock2 where clock1 and clock2 are asynchronous to each other. Now two such consecutive pulses can have minimum two clock cycles of clock1 gap and maximum eight clock cycles of clock1 gap.
What will be the digital logic that can safely transfer these pulses from clock1 to clock2?

a cdc fifo

A repeated 1 0 0 sequence in clock1 domain can't be "safely" transferred, I presume.

A repeated 1 0 0 sequence in clock1 domain can't be "safely" transferred, I presume.

Using a clock domain crossing (CDC) FIFO you can transfer a repeated sequence of 1-0-0 until the FIFO overflows due to the 4:1 write to read ratio. So safely is dependent on the maximum allowed 1-0-0 repeated burst sequence.

My original post was based on the assumption that the aggregate ingress rate of pulses in the 200 MHz domain was equal to the outgoing rate in the 50 MHz domain. If there was some distribution function of the 2-8 clock gaps a determination of "safely" could be definitively determined along with the required FIFO depth.

I completely agree. The problem is the lack of a clear specfication.

Is it presumed that 50MHz is derived from the 200MHz domain, so that they are harmonically synchronous but asynchronous in phase?
Then we can ignore aliasing frequency effects.

Is it "safe" to assume that only pulse count is being transferred or is it the sequential pattern?

Is it "safe" to assume each pulse has the same width as the clock with some small latency?

It looks to be a purely academic question.

It looks to be a purely academic question.
It looks more like an interview question...given the other questions posted by sun_ray today.

Either sun_ray is attempting to pass an interview using edaboard and a mobile phone ;-) or he's conducting interviews for those "jobs" he keeps posting in the job section and needs interview question answers, so they can tell if the interviewee answered the questions correctly.

Might be easier to have the interviewee get grilled by the edaboard members with over 500 helps :thinker:

Is it presumed that 50MHz is derived from the 200MHz domain, so that they are harmonically synchronous but asynchronous in phase?
Then we can ignore aliasing frequency effects.

Is it "safe" to assume that only pulse count is being transferred or is it the sequential pattern?

Is it "safe" to assume each pulse has the same width as the clock with some small latency?

It looks to be a purely academic question.

NO 50 MHz and 200 Mhz are completely independent and hence asynchronous to each other. So 50MHz is not derived from the 200MHz domain.

Pulses are being generated in 200 Mhz clcok domain so its width will be 5 ns. It is the pulse only that is wanted toi be transferred safely to another clock domain.

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a cdc fifo

That we know that it will work .But that is not a cost effective good solution.

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I completely agree. The problem is the lack of a clear specfication.

Where is the lack? Please let us know so that I can clarify.

The problem clearly states that pulses needs to be transferred from clock1 domain to clock2 domain and two consecutive such pulses in clock1 domain can have minimum two clock cycles gap and maximum 8 clock cycles gap. So problem clearly states how these pulses are being generated in clock1 domain. Now these pulses whenever generated in clock domain needs to be transferred to clock2 domain and hence what digital logic will be necessary is the question.

We are looking for a better solution than a fifo.

Without additional constraints, there's no other or even better solution than a dc fifo.

As ads-ee explained, you can't transfer more than 1 pulse per 20 ns on average, or you'll lose pulses. A more exact specification of expectable pulse sequences is necessary to define the fifo depth.

Without additional constraints, there's no other or even better solution than a dc fifo.

As ads-ee explained, you can't transfer more than 1 pulse per 20 ns on average, or you'll lose pulses. A more exact specification of expectable pulse sequences is necessary to define the fifo depth.

Specification about the pulse sequence is clear. The gap between two consecutive pulses in clock1 domain can be minimum 2 clock cycles and maximum 8 clock cycles. So the gap between to consecutive pulses can be 2 or 3 or 4 or 5 or 6 or 7 or 8 clock cycles of clock1. Is it clear now? If not clear please let me know so that I can clarify.

How do you say even using an asynchronous fifo we cannot transfer more than 1 pulse per 20 ns on average?

Specification about the pulse sequence is clear. The gap between two consecutive pulses in clock1 domain can be minimum 2 clock cycles and maximum 8 clock cycles. So the gap between to consecutive pulses can be 2 or 3 or 4 or 5 or 6 or 7 or 8 clock cycles of clock1. Is it clear now? If not clear please let me know so that I can clarify.

How do you say even using an asynchronous fifo we cannot transfer more than 1 pulse per 20 ns on average?

How is it clear? You must not know how to write specifications if you think that was clear...

For instance.
• what is the ppm accuracy of both the 200 MHz and the 50 MHz?
• what is the gap duration distribution of the pulses in the 200 MHz domain?
• what is the maximum contiguous sequence of a gap duration of 2?
To just to name a few of the most obvious specifications that are missing.

And FvM is saying you can't deal with more than 1 pulse per 20 ns on average as there are 4 clock cycle of 200 MHz for every 1 clock cycle of 50 MHz. This brings up the issue in my second bullet...if suppose four 2-cycle gap pulse occur together...

as you can see there are more pulses than there are 50 MHz clock cycles and the longer you keep generating 2-cycle gap pulses the more storage you need to not lose any pulses.

If on average there is exactly one pulse per 20 ns, then if the 200 MHz clock is +ppm faster and the 50 MHz is +0ppm to -ppm slower than eventually pulses will have to be dropped as the clocks are not an exact 4:1 ratio. What is the mitigation scheme for that?

It makes me think that there isn't a true senior level lead engineer on the project, otherwise such a technical lead would have said use a CDC FIFO. And if the aggregate rate is exactly one pulse per 20 ns then that same technical lead would have said we have to use a 200 MHz and 50 MHz that are frequency locked as any frequency drift in the wrong direction will eventually result in a missed pulse.

How is it clear? You must not know how to write specifications if you think that was clear...

For instance.
• what is the ppm accuracy of both the 200 MHz and the 50 MHz?
• what is the gap duration distribution of the pulses in the 200 MHz domain?
• what is the maximum contiguous sequence of a gap duration of 2?
To just to name a few of the most obvious specifications that are missing.

And FvM is saying you can't deal with more than 1 pulse per 20 ns on average as there are 4 clock cycle of 200 MHz for every 1 clock cycle of 50 MHz. This brings up the issue in my second bullet...if suppose four 2-cycle gap pulse occur together...
View attachment 119370
as you can see there are more pulses than there are 50 MHz clock cycles and the longer you keep generating 2-cycle gap pulses the more storage you need to not lose any pulses.

If on average there is exactly one pulse per 20 ns, then if the 200 MHz clock is +ppm faster and the 50 MHz is +0ppm to -ppm slower than eventually pulses will have to be dropped as the clocks are not an exact 4:1 ratio. What is the mitigation scheme for that?

It makes me think that there isn't a true senior level lead engineer on the project, otherwise such a technical lead would have said use a CDC FIFO. And if the aggregate rate is exactly one pulse per 20 ns then that same technical lead would have said we have to use a 200 MHz and 50 MHz that are frequency locked as any frequency drift in the wrong direction will eventually result in a missed pulse.

The ****

I do not know the ppm difference. It is also not needed. The clock1 and clock2 are async to each other are sufficient. I will like to know how ppm difference helps here. The gap duration distribution of the pulses in the 200 MHz domain is clear, it is mimimum of 2 clock cycles and maximum of 8 clock cycles of clock1. What do you mean by * what is the maximum contiguous sequence of a gap duration of 2???

The spec is clear and we are looking for a better solution than a cdc fifo.

The ****

I do not know the ppm difference. It is also not needed. The clock1 and clock2 are async to each other are sufficient. I will like to know how ppm difference helps here. The gap duration distribution of the pulses in the 200 MHz domain is clear, it is mimimum of 2 clock cycles and maximum of 8 clock cycles of clock1. What do you mean by * what is the maximum contiguous sequence of a gap duration of 2???

The spec is clear and we are looking for a better solution than a cdc fifo.

Fine, I now understand you know everything about how to write a clear spec and I know nothing about what information is still needed. I guess, since you said so with a four letter bad word that my help is not needed or appreciated. I'll just let you and the rest of your expert team handle everything on your own from now on.

I can see that I don't know as much about engineering as you do, so I bow to your superior skills and will avoid contradicting you in the future, Thank you for putting me in my place.

You could implement handshaking..(I've not done it myself)

Also these flame wars make me a sad panda

You could implement handshaking..(I've not done it myself)

Also these flame wars make me a sad panda

Huh? I'm not flaming anyone. I asked some valid questions in post #11. If the OP doesn't want my help and wants to flame me after I ask those questions, then I don't need to help them anymore. My points in post #11 regardless of their very rude discounting of them will be the problems that they will inevitably run into and find that they should have accounted for from the start or if they are not an issue then the specification should reflect that by defining the pulse rate across the interface and the pulse distribution (if there is one). I asked for this information but was reprimanded in an arrogant fashion.

My advice has been ignored by sun_ray before. This is the first time they seem to show that I'm not competent enough to tell them about something they should know about (how ppm might affect a transfer when transferring across a pseudo synchronous interface) and they basically tell me I don't know what I'm talking about. My take on this is why give advice to an "expert" that doesn't want said advice.

No flames here, maybe a heavy dose of sarcasm though.

wesleytaylor, please review the discussion and find out yourself whether sun_ray's questions have been answered seriously or not. Unfortunately he either doesn't understand the essential point or prefers to ignore it.

Pulses are coming from a domain with 200 Mhz clock1 to a domain of 50 Mhz clock2 where clock1 and clock2 are asynchronous to each other. Now two such consecutive pulses can have minimum two clock cycles of clock1 gap and maximum eight clock cycles of clock1 gap.
What will be the digital logic that can safely transfer these pulses from clock1 to clock2?
What is the minimum pulse width? T= 1/f1 with min gap = 2/f1 and max gap 8/f1 thus pulse frequency f=1/(1+2) *f1 to 1/(1+8) *f1
What is the output format ?
....serial? not enough bandwidth
.... parallel? what format?

What is the purpose? just count pulses only? or duplicate the pattern at a slower rate? ( the latter cannot be sustained)

the problem is "safely transfer" is not a engineering measurable parameter. It is a vague qualitative riddle.

What is the minimum pulse width? T= 1/f1 with min gap = 2/f1 and max gap 8/f1 thus pulse frequency f=1/(1+2) *f1 to 1/(1+8) *f1
What is the output format ?
....serial? not enough bandwidth
.... parallel? what format?

What is the purpose? just count pulses only? or duplicate the pattern at a slower rate? ( the latter cannot be sustained)

the problem is "safely transfer" is not a engineering measurable parameter. It is a vague qualitative riddle.

Pulses are being generated in clock1 domain. So It has the width of 2.5 ns.

In a CDC problem safely transferring the pulses means that when these pulses reach clock2 domain then they do not cause any problem that can arise die to cdc.

Pulses are being generated in clock1 domain. So It has the width of 2.5 ns.

In a CDC problem safely transferring the pulses means that when these pulses reach clock2 domain then they do not cause any problem that can arise die to cdc.

I've already told you what is required to even start coming up with a solution, but you've already told me to take a hike as in your team's and your own expert opinion have discounted my questions as being irrelevant (refer to #12).

Its obvious I know what your waveform looks like or did you ignore my drawing in post #11? If you waveform can never have that sequence then what is the exact sequence of pulses that the circuit will be expected to deal with. And stop giving the same rubbish answer of it can have gaps of 2 to 8 between pulses. I ALREADY KNOW THAT! (can you hear me!? I'm shouting in hopes that you finally will).

The pattern of pulse spacing (gaps of 2 to 8) and the number of each kind 2,3,4,5,6,7,or 8 in any given set time interval is important regardless of whether you believe me or not. If the pulse gaps are in a random distribution then the average gap is 5. If they aren't random but predictable then draw out the sequence until it repeats and show us what the pulse sequence looks like. Don't tell me the sequence of pulses is: 2 then 3 then 4 ... then 7 then 8 then repeating starting with 2 again. If that is the case then all this arguing is due to poor communication skills and not using a picture or an example to clarify the sequence back at say post #8 or #10.

I'm not even sure why I'm bothering to respond again...maybe I just feel sorry for the walls of your office. :bang:

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Pulses are coming from a domain with 200 Mhz clock1
Pulses are being generated in clock1 domain. So It has the width of 2.5 ns.

I just noticed this discrepancy does the 2.5ns pulse width mean you aren't even producing the pulses off of the 200 MHz using a register. Are you generating the pulses from some sort of gated clock?

Pulses are being generated in clock1 domain. So It has the width of 2.5 ns.

In a CDC problem safely transferring the pulses means that when these pulses reach clock2 domain then they do not cause any problem that can arise due to cdc.

So in other words you have a run length limited (RLL) serial stream using a 200MHz gated clock & data in one signal with spacing (2,8) You want to store the data out and retrieve it at a 50MHz rate.

Is the 200MHz sync clock also provided?

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